1 Silicon Issue Summary

Legend

-: Erratum is not applicable.
X: Erratum is applicable.


Peripheral	Short Description	Valid for Silicon Revision
Peripheral	Short Description	Rev. A6⁽¹⁾	Rev. A7	Rev. A8	Rev. AB
Device	Some Reserved Fuse Bits Are ‘`1`’	X	X	X	X
	Endurance of Flash Memory Cell is Lower than Specified	X	X	X	X
	CRC Check During Reset Initialization Is not Functional	X	X	X	-
	Write Operation Lost if Consecutive Writes to Specific Address Spaces	X	X	X	X
CCL	The LINK Input Source Selection for LUT3 Is not Functional on 28- and 32-Pin Devices	X	X	X	X
CLKCTRL	PLL Status not Working as Expected	X	X	X	X
DAC	DAC Output Buffer Lifetime Drift	X	X	X	X
EVSYS	Port Pins PB[7:6] and PE[7:4] Are not Connected to the Event System	X	X	X	X
NVMCTRL	Flash Mapping Into Data Space not Working Properly	X	X	X	X
	Flash Multi-Page Erase Can Erase Write Protected Section	X	X	X	X
	NVM_EEPROM_ERASE Command does Not Respect Write Protect	X	X	X	X
PORT	Digital Input on Pin Automatically Disabled When Pin Selected for Analog Input	X	X	X	X
RSTCTRL	BOD Registers not Reset When UPDI Is Enabled	X	X	X	X
SPI	SSD Bit Must Be Set When SPIROUTE Value = NONE	X	X	X	X
TCA	TCA1 Pinout Alternative 2 and 3 not Functional	X	X	X	X
TCA	Restart Will Reset Counter Direction in NORMAL and FRQ Mode	X	X	X	X
TCB	CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM Mode	X	X	X	X
TCD	Asynchronous Input Events not Working When TCD Counter Prescaler Is Used	X	X	X	X
	CMPAEN Controls All WOx for Alternative Pin Functions	X	X	X	X
	Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is `0` or Dual Slope Mode is Used	X	X	X	X
TWI	The Output Pin Override Does not Function as Expected	X	X	X	X
	The 50 ns and 300 ns SDA Hold Time Selection Bits Are Swapped	X	X	X	X
	Flush Non-Functional	X	X	X	X
USART	Open-Drain Mode Does not Work When TXD Is Configured as Output	X	X	X	X
	Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode	X	X	X	X
	Receiver Non-Functional after Detection of Inconsistent Synchronization Field	X	X	X	X
ZCD	All ZCD Output Selection Bits Are Tied to the ZCD0 Bit	X	X	X	X

Note:

This revision is the initial release of the silicon.