2.8 Writing Configuration Bits

The procedure for writing Configuration bits is similar to the procedure for writing code memory.

To change the values of the Configuration bits once they have been programmed, the device must be erased, as described in Erasing Program Memory, and reprogrammed to the desired value.

Table 2-7 provides the ICSP programming details for writing the Configuration bits.

The code protection can be enabled by programming ‘0’ in the code protection Configuration bits. In order to verify the data by reading the Configuration bits after performing the write, the code protection bits should initially be programmed to ‘1’ to ensure that the verification can be performed properly. After verification is finished, the code protection bits can be programmed to ‘0’ by using a word write to the appropriate Configuration register.

Table 2-7. Serial Instruction Execution for Writing Configuration Words
Command (Binary)Data (Hex)Description

Step 1: Exit the Reset vector.

0000

0000

0000

0000

0000

0000

0000

000000

000000

000000

040200

000000

000000

000000

NOP

NOP

NOP

GOTO 0x200

NOP

NOP

NOP

Step 2: Initialize the TBLPAG register for writing to the latches.

0000

0000

200FAC

8802AC

MOV #0xFA, W12

MOV W12, TBLPAG

Step 3: Load W0:W1 with the next two Configuration Words to program.

0000

0000

0000

0000

2xxxx0

2xxxx1

2xxxx2

2xxxx3

MOV #<Config1 lower word data>, W0

MOV #<Config1 upper word data>, W1

MOV #<Config2 lower word data>, W2

MOV #<Config2 upper word data>, W3

Step 4: Set the Write Pointer (W3) and load the write latches.

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

EB0300

000000

BB0B00

000000

000000

BB9B01

000000

000000

BB0B02

000000

000000

BB9B03

000000

000000

CLR W6

NOP

TBLWTL W0, [W6]

NOP

NOP

TBLWTH W1, [W6++]

NOP

NOP

TBLWTL W2, [W6]

NOP

NOP

TBLWTH W3, [W6++]

NOP

NOP

Step 5: Set the NVMADRU/NVMADR register pair to point to the correct Configuration Word address.

0000

0000

0000

0000

2xxxx4

2xxxx5

884694

8846A5

MOV #DestinationAddress<15:0>, W4

MOV #DestinationAddress<23:16>, W5

MOV W4, NVMADR

MOV W5, NVMADRU

Step 6: Set the NVMCON register to program two instruction words.

0000

0000

0000

0000

0000

24001A

000000

88468A

000000

000000

MOV #0x4001, W10

NOP

MOV W10, NVMCON

NOP

NOP

Step 7: Initiate the write cycle.

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

200551

8846B1

200AA1

8846B1

A8E8D1

000000

000000

000000

000000

000000

MOV #0x55, W1

MOV W1, NVMKEY

MOV #0xAA, W1

MOV W1, NVMKEY

BSET NVMCON, #WR

NOP

NOP

NOP

NOP

NOP

Step 8: Generate clock pulses for the program operation to complete until the WR bit is cleared.

0000

0000

0000

0000

0000

0001

0000

0000

0000

0000

0000

0000

0000

000000

804680

000000

887E60

000000

<VISI>

000000

000000

000000

040200 000000

000000

000000

NOP

MOV NVMCON, W0

NOP

MOV W0, VISI

NOP

Clock out contents of the VISI register.

NOP

NOP

NOP

GOTO 0x200

NOP

NOP

NOP

Repeat until the WR bit is cleared.

Step 9: Repeat Steps 3-8 until all Configuration registers are programmed.