2.7 Writing Code Memory
Figure 2-7 shows a high-level overview for writing to the code memory.
Figure 2-8 provides the ICSP programming details for writing the code memory.
Code memory is written two instruction words at a time. Two words are loaded into the write latches, located at 0xFA0000 and 0xFA0002, using the packed data format shown in Figure 2-7. The destination address is loaded into the NVMADR and NVMADRU registers. Next, the write cycle is initiated by setting the WREN bit in the NVMCON register. The WR bit in NVMCON will be cleared in hardware once the double-word write is complete. This process is repeated for all memory locations to be programmed.
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Command (Binary) |
Data (Hex) |
Description |
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| Step 1: Exit the Reset vector. | ||
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| Step 2: Initialize the TBLPAG register for writing to the latches. | ||
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Step 3: Load W0:W2 with the next two packed instruction words to program. | ||
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| Step 4: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches. | ||
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Step 5: Set the NVMADRU/NVMADR register pair to point to the correct address. | ||
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| Step 6: Set the NVMCON register to program two instruction words. | ||
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| Step 7: Initiate the write cycle. | ||
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| Step 8: Generate clock pulses for the program operation to complete until the WR bit is cleared. | ||
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000000
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Clock out contents of the VISI register.
Repeat until the WR bit is cleared. |
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Step 9: Repeat Steps 3-8 until all code memory has been programmed. | ||