2.2 Entering ICSP Mode

As shown in Figure 2-2, entering ICSP Program/Verify mode requires three steps:

  1. MCLR is briefly driven high, then low (P21).
  2. A 32-bit key sequence is clocked into PGEDx. An interval of at least P18 must elapse before presenting the key sequence on PGEDx.
  3. MCLR is held low during a specified period, P19, and then driven high.
  4. After a P7 + 5 * P1 delay, five clock pulses must be generated on the PGECx pin.
Note: If a capacitor is present on the MCLR pin, the high time for entering ICSP mode can vary.

The key sequence is a specific 32-bit pattern, ‘0100 1101 0100 0011 0100 1000 0101 0001’ (more easily remembered as 0x4D434851 in hexadecimal). The device will enter ICSP mode only if the sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first.

On successful entry, the program memory can be accessed and programmed in serial fashion.

Figure 2-2. Entering ICSP™ Mode