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SmartFusion 2 and IGLOO 2 FPGA Board and Layout Design Guidelines
SmartFusion 2 and IGLOO 2 FPGA Board and Layout Design Guidelines
  1. Home
  2. 4 Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs
  3. 4.2 Creating Schematic Symbols with User Defined Pin Names
  4. 4.2.3 Generating a Capture Schematic Symbol
  • Introduction
  • 1 Design Considerations
  • 2 Layout Guidelines for SmartFusion 2 and IGLOO 2-Based Board Design
  • 3 PCB Inspection Guidelines
  • 4 Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs
    • 4.1 Creating Schematic Symbols using Pin Assignment Tables (PAT)
    • 4.2 Creating Schematic Symbols with User Defined Pin Names
      • 4.2.1 Exporting Pin Information from the Libero Design
      • 4.2.2 Preparing the Pin List for Import into OrCAD Capture CIS
      • 4.2.3 Generating a Capture Schematic Symbol
  • 5 Board Design and Layout Checklist
  • 6 Appendix A: Special Layout Guidelines—Crystal Oscillator
  • 7 Appendix B: Stack-Up
  • 8 Appendix C: Dielectric Material
  • 9 Appendix D: Power Integrity Simulation Topology
  • 10 Appendix E: X-Ray Inspection
  • 11 Revision History
  • Microchip FPGA Support
  • Microchip Information

4.2.3 Generating a Capture Schematic Symbol

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See Generating a OrCAD Capture Schematic Symbol.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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