11 Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Revision Date Description
G 11/2023 Revised the figure and associated text in section 1.9.1 Internal Clamp Diode Circuitry.
F 10/2023 Added Table 1-18.
E 07/2022 The following is a summary of changes made in this revision.
D 06/2022 The following is a summary of changes made in this revision.
C 01/2022 The following is a summary of changes made in this revision.
B 11/2021 The following is a summary of changes made in this revision.
A 09/2021

The following is a summary of changes made in this revision.

15.0 10/2020

The following is a summary of changes made in this revision.

  • Renamed Table 1-4 to Table 1-7 as “Requirements for Bank Supplies”.
  • Information about I/O glitch at auto-update during POR was added, see 1.2.4 I/O Glitch at Auto-Update During POR.
  • Updated the note in 1.1 Power Supplies to include Aux. PLL PCIe Supply in the power supply settings description for PLLs.
  • Internal pull-up clamp diode is not present in MSIO. Hence, removed MSIO from Figure 1-20.
  • In Table 5-1 (Design Checklist → Power Supplies → VDDI Bank Supplies), added reference to Table 1-4 to Table 1-7 for verifying the requirements for VDDI Bank supplies.
  • Updated the pull-down resistor requirement to 150 Ω for the xDDR_IMP_CALIB_ECC pin of LPDDR and DDR2 interface. See Figure 1-16 and Figure 1-17.
14.0 The following is a summary of changes made in revision 14.0 of this document.
  • Information about I/O glitches during power-up, power-down, and on blank devices was updated. For more information, see I/O Glitch.
  • A figure was added to illustrate SPI initiator mode programming. For more information, see SPI Master Programming
  • Information about simultaneous switching noise support was added. For more information, see Simultaneous Switching Noise.

  • The design checklist from CL0034: SmartFusion2/IGLOO2 Hardware Board Design Checklist was merged into this document.

  • List of device-package combinations that do not have SERDES_x_VDD pins was added. For more information, see Table 1-1.

  • Design checklist was added in Board Design and Layout Checklist.

  • Information about the de-coupling capacitor and SmartFusion2/IGLOO2 placement was added in Component Placement.

  • Figures were updated in LPDDR and DDR2 Design and DDR3 Guidelines.

13.0

The following is a summary of changes made in revision 13.0 of this document.

12.0

The following is a summary of changes made in revision 12.0 of this document.

  • Recommended bank supplies are updated for the FG484 package. See Table 1-5.
  • Recommended bank supplies are updated for VF400 and FCS325 Packages. See Table 1-6.
  • Recommended bank supplies are updated for VF256 and TQ144 Packages. See Table 1-7.

  • Added a note about DQ pins that all 4- and 8-bit pins are interchangeable in LPDDR, DDR2, and DDR3 memories. See Figure 1-16.

  • Added that the SERDES_x_L[01/23]_VDDAPLL pin supports only 2.5 V, and removed 1.2 V references from all occurrences. For more information, see figure 1 and Table 1-7.

  • AC394: Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design was added as a part of Board Design guidelines itself.

11.0

The following is a summary of changes made in revision 11.0 of this document.

  • The filter circuit for SERDES_x_VDD was removed. Even if it was used in the board design previously, it does not affect the functionality of the board. See Figure 1-1.
  • Information about VDDI2 was updated. See Table 1-6 and Table 1-7.
  • Information about reset circuit was updated. see Reset Circuit.

  • Changed the document to the new template.

10.0

The following is a summary of the changes made in revision 10.0 of this document.

9.0

The following is a summary of the changes made in revision 9.0 of this document.

  • Updated Figure 1-1 (SAR 72533).
  • Added CCC_PLL_VDDA and MSS_xDDR_PLL_VDDA details under Power Supplies (SAR 72533).
  • Deleted the RC Values for Filter Circuitry table (SAR 72533).

  • Added the M2S060T/M2GL060T device column in Table 1-7(SAR 70484).

8.0

The following is a summary of the changes made in revision 8.0 of this document.

7.0

The following is a summary of the changes made in revision 7.0 of this document.

6.0

The following is a summary of the changes made in revision 6.0 of this document.

5.0

The following is a summary of the changes made in revision 5.0 of this document.

4.0

The following is a summary of the changes made in revision 4.0 of this document.

3.0

The following is a summary of the changes made in revision 3.0 of this document.

2.0

The following is a summary of the changes made in revision 2.0 of this document.

1.0

The following is a summary of the changes made in revision 1.0 of this document.