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SmartFusion 2 and IGLOO 2 FPGA Board and Layout Design Guidelines
Introduction
1 Design Considerations
1.1 Power Supplies
1.2 I/O Glitch
1.3 Limiting VDD Surge Current
1.4 Clocks
1.5 Reset Circuit
1.6 Device Programming
1.7 SerDes
1.8 LPDDR, DDR2, and DDR3
1.9 User I/O and Clock Pins
1.10 Obtaining a Two-Rail Design for Non-SerDes Applications
1.11 Configuring Pins in Open Drain
1.12 Brownout Detection (BOD)
1.13 Simultaneous Switching Noise
2 Layout Guidelines for SmartFusion 2 and IGLOO 2-Based Board Design
2.1 Power Supply
2.2 Core Supply (VDD)
2.3 SerDes
2.4 DDR
2.5 PLL
2.6 I/O Power Supply
2.7 Programming Power Supply (VPP or VCCENVM)
2.8 High-Speed Serial Link (SerDes)
2.9 Considerations for Simulation
2.10 DDR3 Layout Guidelines
2.11 References
3 PCB Inspection Guidelines
4 Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs
4.1 Creating Schematic Symbols using Pin Assignment Tables (PAT)
4.2 Creating Schematic Symbols with User Defined Pin Names
5 Board Design and Layout Checklist
5.1 Prerequisites
5.2 Design Checklist
5.3 Layout Checklist
6 Appendix A: Special Layout Guidelines—Crystal Oscillator
7 Appendix B: Stack-Up
8 Appendix C: Dielectric Material
9 Appendix D: Power Integrity Simulation Topology
10 Appendix E: X-Ray Inspection
11 Revision History
Microchip FPGA Support
Microchip Information
The Microchip Website
Product Change Notification Service
Customer Support
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System
Worldwide Sales and Service

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