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SmartFusion 2 and IGLOO 2 FPGA Board and Layout Design Guidelines
SmartFusion 2 and IGLOO 2 FPGA Board and Layout Design Guidelines
  1. Home
  2. 5 Board Design and Layout Checklist
  3. 5.1 Prerequisites
  • Introduction
  • 1 Design Considerations
  • 2 Layout Guidelines for SmartFusion 2 and IGLOO 2-Based Board Design
  • 3 PCB Inspection Guidelines
  • 4 Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs
  • 5 Board Design and Layout Checklist
    • 5.1 Prerequisites
    • 5.2 Design Checklist
    • 5.3 Layout Checklist
  • 6 Appendix A: Special Layout Guidelines—Crystal Oscillator
  • 7 Appendix B: Stack-Up
  • 8 Appendix C: Dielectric Material
  • 9 Appendix D: Power Integrity Simulation Topology
  • 10 Appendix E: X-Ray Inspection
  • 11 Revision History
  • Microchip FPGA Support
  • Microchip Information

5.1 Prerequisites

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Ensure to read following sections:

  • 1 Design Considerations
  • 2 Layout Guidelines for SmartFusion 2 and IGLOO 2-Based Board Design
The SmartFusion2 and IGLOO2 families consists of FPGAs ranging from densities of 6K to 100K Logic Elements (LE).
Important: This checklist is intended as a guideline only.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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