2.2.2 Scan
The scan list conversions defined in the ADCCSS1 register will restart without finishing the current scan list and does not generate an EOSRDY bit (ADCCON2[29]) end of scan interrupt status if a new trigger event from the STRGSRC[4:0] bits (ADCCON1[20:16]) trigger source occurs before the scan list completion on the shared ADC core.
Work Around:
Ensure that the STRGSRC[4:0] bits trigger source repetition rate.
Affected Silicon Revisions
PIC32CX1012BZ25048/WBZ451/WBZ451HA0 | A2 | |||||
---|---|---|---|---|---|---|
X | X |
A2 | |||||
---|---|---|---|---|---|
X |