40.6.2 1588 Timestamp Unit
The timestamp unit (TSU) consists of a timer and registers to capture the time at which PTP event frames cross the message timestamp point. An interrupt is issued when a capture register is updated.
The 1588 timestamp unit (TSU) is implemented as a 102-bit timer.
The 48 upper bits [101:54] of the timer count seconds and are accessible in the GMAC 1588 Timer Seconds High Register (GMAC_TSH) and GMAC 1588 Timer Seconds Low Register (GMAC_TSL).
The 30 lower bits [53:24] of the timer count nanoseconds and are accessible in the GMAC 1588 Timer Nanoseconds Register (GMAC_TN). The lowest 24 bits [23:0] of the timer count sub-nanoseconds and are accessible in the GMAC 1588 Timer Increment Sub-nanoseconds Register (GMAC_TISUBN).
The 54 lower bits roll over when they have counted to one second. The timer increments by a programmable period (to approximately 58.6 attoseconds resolution) with each clock period and can also be adjusted in 1 ns resolution (incremented or decremented) through APB register accesses.
The clock used can be MCK or GMAC0_TSU that can be connected to a faster clock to increase timestamp accuracy.
The amount by which the timer increments each clock cycle is controlled by the Timer Increment registers (GMAC_TI).
Bits 7:0 are the default increment value in nanoseconds and an additional 24 bits of sub-nanosecond resolution are available using the Timer Increment Subnanoseconds register (GMAC_TISUBN).
If the rest of the register is written with zero, the timer increments by the value in [7:0], plus the value of GMAC_TISUBN, at each clock cycle.
GMAC_TISUBN allows a resolution of approximately 58.6 attoseconds.
Bits 15:8 of GMAC_TI is the alternative increment value in nanoseconds and bits 23:16 are the number of increments after which the alternative increment value is used. If 23:16 are zero, then the alternative increment value will never be used.
Taking the example of 10.2 MHz, there are 102 cycles every ten microseconds or 51 every five microseconds. So a timer with a 10.2 MHz clock source is constructed by incrementing by 98 ns for fifty cycles and then incrementing by 100 ns (98 × 50 + 100 = 5000). This is programmed by setting the 1588 Timer Increment register to 0x00326462.
For a 49.8 MHz clock source it would be 20 ns for 248 cycles followed by an increment of 40 ns (20 × 248 + 40 = 5000) programmed as 0x00F82814.
Having eight bits for the “number of increments” field allows frequencies up to 50 MHz to be supported with 200 kHz resolution.
Without the alternative increment field, the period of the clock would be limited to an integer number of nanoseconds, resulting in supported clock frequencies of 8, 10, 20, 25, 40, 50, 100, 125, 200 and 250 MHz.
There are additional registers that capture the time at which PTP event frames are transmitted and received. An interrupt is issued when these registers are updated. The TSU timer count value can be compared to a programmable comparison value. For the comparison, the bits of the seconds value and the upper 22 bits of the nanoseconds value are used.
An interrupt can also be generated (if enabled) when the TSU timer count value and comparison value are equal, mapped to bit 29 of the Interrupt Status register.
A signal (GTSUCOMP) is provided to indicate when the TSU timer count value is equal to the comparison value stored in the TSU timer comparison value registers (0x0DC, 0x0E0, and 0x0E4).
