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Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, Graphics Interface, Ethernet 10/100, IEEE®1588, CAN-FD, USB, AEC-Q100 Grade 2
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40
Ethernet MAC (GMAC)
40.6
Functional Description
40.6.5
Transmit Scheduling Algorithm
Description
Features
1
Configuration Summary
2
Block Diagram
3
Signal Description
4
Microchip Recommended Power Management Solutions
5
Automotive Quality Grade
6
Safety and Security Features
7
Pinout
8
Power Considerations
9
Memories
10
Event System
11
System Controller
12
Peripherals
13
Chip Identifier (CHIPID)
14
Cortex-A5 Processor (ARM)
15
L2 Cache Controller (L2CC)
16
Debug and Test Features
17
Standard Boot Strategies
18
CPU System Bus Matrix (CPUMX)
19
Matrix (H64MX/H32MX)
20
Special Function Registers (SFR)
21
Special Function Registers Backup (SFRBU)
22
Advanced Interrupt Controller (AIC)
23
Watchdog Timer (WDT)
24
Reset Controller (RSTC)
25
Shutdown Controller (SHDWC)
26
Periodic Interval Timer (PIT)
27
Real-time Clock (RTC)
28
System Controller Write Protection (SYSCWP)
29
Slow Clock Controller (SCKC)
30
Peripheral Touch Controller (PTC)
31
Low Power Asynchronous Receiver (RXLP)
32
Clock Generator
33
Power Management Controller (PMC)
34
Parallel Input/Output Controller (PIO)
35
External Memories
36
DDR-SDRAM Controller (MPDDRC)
37
Static Memory Controller (SMC)
38
DMA Controller (XDMAC)
39
LCD Controller (LCDC)
40
Ethernet MAC (GMAC)
40.1
Description
40.2
Embedded Characteristics
40.3
Block Diagram
40.4
Signal Interfaces
40.5
Product Dependencies
40.6
Functional Description
40.6.1
Media Access Controller
40.6.2
1588 Timestamp Unit
40.6.3
Direct Memory Access Interface
40.6.4
MAC Transmit Block
40.6.5
Transmit Scheduling Algorithm
40.6.5.1
Introduction
40.6.5.2
802.1Qav Support - Credit-based Shaping
40.6.5.3
Fixed Priority
40.6.5.4
Deficit Weighted Round Robin (DWRR)
40.6.5.5
Enhanced Transmission Selection (ETS)
40.6.6
MAC Receive Block
40.6.7
Checksum Offload for IP, TCP and UDP
40.6.8
MAC Filtering Block
40.6.9
Broadcast Address
40.6.10
Hash Addressing
40.6.11
Copy all Frames (Promiscuous Mode)
40.6.12
Disable Copy of Pause Frames
40.6.13
VLAN Support
40.6.14
Wake on LAN Support
40.6.15
IEEE 1588 Support
40.6.16
MAC 802.3 Pause Frame Support
40.6.17
MAC PFC Priority-based Pause Frame Support
40.6.18
Energy-efficient Ethernet Support
40.6.19
LPI Operation in the GMAC
40.6.20
PHY Interface
40.6.21
10/100 Operation
40.6.22
Jumbo Frames
40.7
Programming Interface
40.8
Register Summary
41
USB Device High Speed Port (UDPHS)
42
USB Host High Speed Port (UHPHS)
43
Audio Class D Amplifier (CLASSD)
44
Inter-IC Sound Controller (I2SC)
45
Synchronous Serial Controller (SSC)
46
Two-wire Interface (TWIHS)
47
Flexible Serial Communication Controller (FLEXCOM)
48
Universal Asynchronous Receiver Transmitter (UART)
49
Serial Peripheral Interface (SPI)
50
Quad Serial Peripheral Interface (QSPI)
51
Secure Digital MultiMedia Card Controller (SDMMC)
52
Image Sensor Controller (ISC)
53
Controller Area Network (MCAN)
54
Timer Counter (TC)
55
Pulse Density Modulation Interface Controller (PDMIC)
56
Pulse Width Modulation Controller (PWM)
57
Secure Fuse Controller (SFC)
58
Integrity Check Monitor (ICM)
59
Advanced Encryption Standard Bridge (AESB)
60
Advanced Encryption Standard (AES)
61
Secure Hash Algorithm (SHA)
62
Triple Data Encryption Standard (TDES)
63
True Random Number Generator (TRNG)
64
Analog Comparator Controller (ACC)
65
Security Module (SECUMOD)
66
Analog-to-Digital Controller (ADC)
67
Electrical Characteristics
68
Mechanical Characteristics
69
Marking
70
Ordering Information
71
Revision History
Microchip Information
40.6.5 Transmit Scheduling Algorithm
