53.6.16 MCAN Interrupt Line Select Register
The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines.
0: Interrupt assigned to interrupt line MCAN_INT0.
1: Interrupt assigned to interrupt line MCAN_INT1.
Name: | MCAN_ILS |
Offset: | 0x58 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | ARAL | PEDL | PEAL | WDIL | BOL | EWL | |
Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EPL | ELOL | | | DRXL | TOOL | MRAFL | TSWL | |
Access | R/W | R/W | | | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | | | 0 | 0 | 0 | 0 | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TEFLL | TEFFL | TEFWL | TEFNL | TFEL | TCFL | TCL | HPML | |
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RF1LL | RF1FL | RF1WL | RF1NL | RF0LL | RF0FL | RF0WL | RF0NL | |
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 29 – ARAL Access to Reserved Address
Line
Bit 28 – PEDL Protocol Error in Data Phase
Line
Bit 27 – PEAL Protocol Error in Arbitration Phase
Line
Bit 26 – WDIL Watchdog Interrupt Line
Bit 25 – BOL Bus_Off Status Interrupt Line
Bit 24 – EWL Warning Status Interrupt Line
Bit 23 – EPL Error Passive Interrupt Line
Bit 22 – ELOL Error Logging Overflow Interrupt Line
Bit 19 – DRXL Message stored to Dedicated Receive Buffer Interrupt Line
Bit 18 – TOOL Timeout Occurred Interrupt Line
Bit 17 – MRAFL Message RAM Access Failure Interrupt Line
Bit 16 – TSWL Timestamp Wraparound Interrupt Line
Bit 15 – TEFLL Tx Event FIFO Event Lost Interrupt Line
Bit 14 – TEFFL Tx Event FIFO Full Interrupt Line
Bit 13 – TEFWL Tx Event FIFO Watermark Reached Interrupt Line
Bit 12 – TEFNL Tx Event FIFO New Entry Interrupt Line
Bit 11 – TFEL Tx FIFO Empty Interrupt Line
Bit 10 – TCFL Transmission Cancellation Finished Interrupt Line
Bit 9 – TCL Transmission Completed Interrupt Line
Bit 8 – HPML High Priority Message Interrupt Line
Bit 7 – RF1LL Receive FIFO 1 Message Lost Interrupt Line
Bit 6 – RF1FL Receive FIFO 1 Full Interrupt Line
Bit 5 – RF1WL Receive FIFO 1 Watermark Reached Interrupt Line
Bit 4 – RF1NL Receive FIFO 1 New Message Interrupt Line
Bit 3 – RF0LL Receive FIFO 0 Message Lost Interrupt Line
Bit 2 – RF0FL Receive FIFO 0 Full Interrupt Line
Bit 1 – RF0WL Receive FIFO 0 Watermark Reached Interrupt Line
Bit 0 – RF0NL Receive FIFO 0 New Message Interrupt Line