17.5.4 Boot Configuration Word
The Boot Configuration Word comprises the 32 boot configuration bits (see the table Customer Fuse Matrix).
Warning: To avoid any malfunctioning, the user must not write the “DO NOT
USE (DNU)” fuse bits.
| Name: | Boot Configuration Word |
| Reset: | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SECURE_ MODE | DNU | DNU | DNU | DNU | DISABLE_MONITOR | ||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DNU | DISABLE_BSCR | QSPI_XIP_MODE | DNU | DNU | EXT_MEM_BOOT_ENABLE | JTAG_IO_SET[1:0] | |||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| UART_CONSOLE[3:0] | SDMMC_1 | SDMMC_0 | NFC[1:0] | ||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPI_1[1:0] | SPI_0[1:0] | QSPI_1[1:0] | QSPI_0[1:0] | ||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 29 – SECURE_ MODE Enable Secure Boot Mode
| Value | Description |
|---|---|
| 0 | Standard boot sequence |
| 1 | Secure boot sequence |
Bits 25, 26, 27, 28 – DNU DO NOT USE
Bit 24 – DISABLE_MONITOR Disable SAM-BA Monitor
| Value | Description |
|---|---|
| 0 | If no boot file found, launch SAM-BA Monitor. |
| 1 | SAM-BA Monitor never launched. |
Bit 23 – DNU DO NOT USE
Bit 22 – DISABLE_BSCR Disable Read of BSC_CR
| Value | Description |
|---|---|
| 0 | If the BUREG index in the BSC_CR is valid, its data replace Fuse configuration bits. |
| 1 | Does not read BSC_CR content, so the Boot settings are those from the Fuse. |
Bit 21 – QSPI_XIP_MODE Enable XIP Mode on QSPI Flash
| Value | Description |
|---|---|
| 0 | QSPI is accessed in QSPI mode and data copied into internal SRAM. |
| 1 | QSPI is accessed in XIP mode, and the bootstrap directly executed from it. |
Bits 19, 20 – DNU DO NOT USE
Bit 18 – EXT_MEM_BOOT_ENABLE Enable Boot on External Memories
| Value | Description |
|---|---|
| 0 | No external memory boot performed. |
| 1 | External memory boot enabled. |
Bits 17:16 – JTAG_IO_SET[1:0] Pin Selection for JTAG Access
| Value | Name | Description |
|---|---|---|
| 0 | JTAG_IOSET_1 | Use JTAG IO Set 1 |
| 1 | JTAG_IOSET_2 | Use JTAG IO Set 2 |
| 2 | JTAG_IOSET_3 | Use JTAG IO Set 3 |
| 3 | JTAG_IOSET_4 | Use JTAG IO Set 4 |
Bits 15:12 – UART_CONSOLE[3:0] Selects the pins and UART interface used as a console terminal
| Value | Name | Description |
|---|---|---|
| 0 | UART_1_IOSET_1 | Use UART1 IO Set 1 |
| 1 | UART_0_IOSET_1 | Use UART0 IO Set 1 |
| 2 | UART_1_IOSET_2 | Use UART1 IO Set 2 |
| 3 | UART_2_IOSET_1 | Use UART2 IO Set 1 |
| 4 | UART_2_IOSET_2 | Use UART2 IO Set 2 |
| 5 | UART_2_IOSET_3 | Use UART2 IO Set 3 |
| 6 | UART_3_IOSET_1 | Use UART3 IO Set 1 |
| 7 | UART_3_IOSET_2 | Use UART3 IO Set 2 |
| 8 | UART_3_IOSET_3 | Use UART3 IO Set 3 |
| 9 | UART_4_IOSET_1 | Use UART4 IO Set 1 |
| 10 | DISABLED | No console terminal |
| 11 | DISABLED | No console terminal |
| 12 | DISABLED | No console terminal |
| 13 | DISABLED | No console terminal |
| 14 | DISABLED | No console terminal |
| 15 | DISABLED | No console terminal |
Bit 11 – SDMMC_1 Disable SDCard/e.MMC Boot on SDMMC_1
| Value | Description |
|---|---|
| 0 | Boots on SDMMC_1 using SDMMC_1 PIO Set 1. |
| 1 | Disables boot on SDMMC_1. |
Bit 10 – SDMMC_0 Disable SDCard/e.MMC Boot on SDMMC_0
| Value | Description |
|---|---|
| 0 | Boots on SDMMC_0 using SDMMC_0 PIO Set 1. |
| 1 | Disables boot on SDMMC_0. |
Bits 9:8 – NFC[1:0] Select the PIO Set Used for NFC Boot
| Value | Name | Description |
|---|---|---|
| 0 | NFC_IOSET_1 | Use NFC IO Set 1 |
| 1 | NFC_IOSET_2 | Use NFC IO Set 2 |
| 2 | DISABLED | NFC boot is disabled |
| 3 | DISABLED | NFC boot is disabled |
Bits 7:6 – SPI_1[1:0] Select the PIO Set Used for SPI_1 Boot
| Value | Name | Description |
|---|---|---|
| 0 | SPI_1_IOSET_1 | Use SPI_1 IO Set 1 |
| 1 | SPI_1_IOSET_2 | Use SPI_1 IO Set 2 |
| 2 | SPI_1_IOSET_3 | Use SPI_1 IO Set 3 |
| 3 | DISABLED | SPI boot is disabled |
Bits 5:4 – SPI_0[1:0] Select the PIO Set Used for SPI_0 Boot
| Value | Name | Description |
|---|---|---|
| 0 | SPI_0_IOSET_1 | Use SPI_0 IO Set 1 |
| 1 | SPI_0_IOSET_2 | Use SPI_0 IO Set 2 |
| 2 | DISABLED | SPI boot is disabled |
| 3 | DISABLED | SPI boot is disabled |
Bits 3:2 – QSPI_1[1:0] Select the PIO Set Used for QSPI_1 Boot
| Value | Name | Description |
|---|---|---|
| 0 | QSPI_1_IOSET_1 | Use QSPI_1 PIO Set 1 |
| 1 | QSPI_1_IOSET_2 | Use QSPI_1 PIO Set 2 |
| 2 | QSPI_1_IOSET_3 | Use QSPI_1 PIO Set 3 |
| 3 | DISABLED | QSPI_1 boot is disabled |
Bits 1:0 – QSPI_0[1:0] Select the PIO Set Used for QSPI_0 Boot
| Value | Name | Description |
|---|---|---|
| 0 | QSPI_0_IOSET_1 | Use QSPI_0 PIO Set 1 |
| 1 | QSPI_0_IOSET_2 | Use QSPI_0 PIO Set 2 |
| 2 | QSPI_0_IOSET_3 | Use QSPI_0 PIO Set 3 |
| 3 | DISABLED | QSPI_0 boot is disabled |