14.5.3 Cortex-A5 Registers

This view provides 16 ARM core registers, R0 to R15, that include the Stack Pointer (SP), Link Register (LR), and Program Counter (PC). The current execution mode determines the selected set of registers, as shown in the table below. This shows that the arrangement of the registers provides duplicate copies of some registers, with the current register selected by the execution mode. This arrangement is described as banking of the registers, and the duplicated copies of registers are referred to as banked registers.

Table 14-3. Cortex-A5 Modes and Registers Layout
User and System	Monitor	Supervisor	Abort	Undefined	Interrupt	Fast Interrupt
R0	R0	R0	R0	R0	R0	R0
R1	R1	R1	R1	R1	R1	R1
R2	R2	R2	R2	R2	R2	R2
R3	R3	R3	R3	R3	R3	R3
R4	R4	R4	R4	R4	R4	R4
R5	R5	R5	R5	R5	R5	R5
R6	R6	R6	R6	R6	R6	R6
R7	R7	R7	R7	R7	R7	R7
R8	R8	R8	R8	R8	R8	R8_FIQ⁽¹⁾
R9	R9	R9	R9	R9	R9	R9_FIQ⁽¹⁾
R10	R10	R10	R10	R10	R10	R10_FIQ⁽¹⁾
R11	R11	R11	R11	R11	R11	R11_FIQ⁽¹⁾
R12	R12	R12	R12	R12	R12	R12_FIQ⁽¹⁾
R13⁽¹⁾	R13_MON⁽¹⁾	R13_SVC⁽¹⁾	R13_ABT⁽¹⁾	R13_UND⁽¹⁾	R13_IRQ⁽¹⁾	R13_FIQ⁽¹⁾
R14⁽¹⁾	R14_MON⁽¹⁾	R14_SVC⁽¹⁾	R14_ABT⁽¹⁾	R14_UND⁽¹⁾	R14_IRQ⁽¹⁾	R14_FIQ⁽¹⁾
PC	PC	PC	PC	PC	PC	PC

CPSR	CPSR	CPSR	CPSR	CPSR	CPSR	CPSR
	SPSR_MON⁽¹⁾	SPSR_SVC⁽¹⁾	SPSR_ABT⁽¹⁾	SPSR_UND⁽¹⁾	SPSR_IRQ⁽¹⁾	SPSR_FIQ⁽¹⁾

Note:

Mode-specific banked registers.

The core contains one CPSR, and six SPSRs for exception handlers to use. The program status registers:

hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operating mode

N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
Q: cumulative saturation flag
IT: If-Then execution state bits for the Thumb-2 IT (If-Then) instruction
J: Jazelle bit, see the description of the T bit
GE: Greater than or Equal flags, for SIMD instructions
E: Endianness execution state bit. Controls the load and store endianness for data accesses. This bit is ignored by instruction fetches.
- E = 0: Little endian operation
- E = 1: Big endian operation
A: Asynchronous abort disable bit. Used to mask asynchronous aborts.
I: Interrupt disable bit. Used to mask IRQ interrupts.
F: Fast interrupt disable bit. Used to mask FIQ interrupts.
T: Thumb-2 execution state bit. This bit and the J execution state bit, bit [24], determine the instruction set state of the processor, ARM, Thumb-2, Jazelle, or Thumb-2EE.
Mode: five bits to encode the current processor mode. The effect of setting M[4:0] to a reserved value is UNPREDICTABLE.

Table 14-4. Processor Mode vs. Mode Field
Mode	M[4:0]
USR	10000
FIQ	10001
IRQ	10010
SVC	10011
MON	10110
ABT	10111
UND	11011
SYS	11111
Reserved	Other