14.5.3.1 CP15 Coprocessor

Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below:

Cortex-A5
Caches (ICache, DCache and write buffer)
MMU
Security
Other system options

To control these features, CP15 provides 16 additional registers. See the table below.

Table 14-5. CP15 Registers
Register	Name	Read/Write
0	ID Code⁽¹⁾	Read/Unpredictable
0	Cache type⁽¹⁾	Read/Unpredictable
1	Control⁽¹⁾	Read/Write
1	Security⁽¹⁾	Read/Write
2	Translation Table Base	Read/Write
3	Domain Access Control	Read/Write
4	Reserved	None
5	Data fault Status⁽¹⁾	Read/Write
5	Instruction fault status	Read/Write
6	Fault Address	Read/Write
7	Cache and MMU Operations⁽¹⁾	Read/Write
8	TLB operations	Unpredictable/Write
9	Cache lockdown⁽¹⁾	Read/Write
10	TLB lockdown	Read/Write
11	Reserved	None
12	Interrupts management	Read/Write
12	Monitor vectors	Read-only
13	FCSE PID⁽¹⁾	Read/Write
13	Context ID⁽¹⁾	Read/Write
14	Reserved	None
15	Test configuration	Read/Write

Note:

This register provides access to more than one register. The register accessed depends on the value of the CRm field or opcode_2 field.