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Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, Graphics Interface, Ethernet 10/100, IEEE®1588, CAN-FD, USB, AEC-Q100 Grade 2
Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, Graphics Interface, Ethernet 10/100, IEEE®1588, CAN-FD, USB, AEC-Q100 Grade 2
  1. Home
  2. 34 Parallel Input/Output Controller (PIO)
  3. 34.5 Functional Description
  4. 34.5.15 I/O Line Configuration Freeze
  5. 34.5.15.2 Software Freeze
  • Description
  • Features
  • 1 Configuration Summary
  • 2 Block Diagram
  • 3 Signal Description
  • 4 Microchip Recommended Power Management Solutions
  • 5 Automotive Quality Grade
  • 6 Safety and Security Features
  • 7 Pinout
  • 8 Power Considerations
  • 9 Memories
  • 10 Event System
  • 11 System Controller
  • 12 Peripherals
  • 13 Chip Identifier (CHIPID)
  • 14 Cortex-A5 Processor (ARM)
  • 15 L2 Cache Controller (L2CC)
  • 16 Debug and Test Features
  • 17 Standard Boot Strategies
  • 18 CPU System Bus Matrix (CPUMX)
  • 19 Matrix (H64MX/H32MX)
  • 20 Special Function Registers (SFR)
  • 21 Special Function Registers Backup (SFRBU)
  • 22 Advanced Interrupt Controller (AIC)
  • 23 Watchdog Timer (WDT)
  • 24 Reset Controller (RSTC)
  • 25 Shutdown Controller (SHDWC)
  • 26 Periodic Interval Timer (PIT)
  • 27 Real-time Clock (RTC)
  • 28 System Controller Write Protection (SYSCWP)
  • 29 Slow Clock Controller (SCKC)
  • 30 Peripheral Touch Controller (PTC)
  • 31 Low Power Asynchronous Receiver (RXLP)
  • 32 Clock Generator
  • 33 Power Management Controller (PMC)
  • 34 Parallel Input/Output Controller (PIO)
    • 34.1 Description
    • 34.2 Embedded Characteristics
    • 34.3 Block Diagram
    • 34.4 Product Dependencies
    • 34.5 Functional Description
      • 34.5.1 I/O Line Configuration Method
      • 34.5.2 Pull-Up and Pull-Down Resistor Control
      • 34.5.3 General Purpose or Peripheral Function Selection
      • 34.5.4 Output Control
      • 34.5.5 Synchronous Data Output
      • 34.5.6 Open-Drain Mode
      • 34.5.7 Output Line Timings
      • 34.5.8 Inputs
      • 34.5.9 Input Glitch and Debouncing Filters
      • 34.5.10 Input Edge/Level Interrupt
      • 34.5.11 Interrupt Management
      • 34.5.12 I/O Lines Lock
      • 34.5.13 Programmable I/O Drive
      • 34.5.14 Programmable Schmitt Trigger
      • 34.5.15 I/O Line Configuration Freeze
        • 34.5.15.1 Introduction
        • 34.5.15.2 Software Freeze
          • 34.5.15.2.1 Physical Freeze
          • 34.5.15.2.2 Interrupt Freeze
      • 34.5.16 Register Write Protection
    • 34.6 I/O Lines Programming Example
    • 34.7 Register Summary
  • 35 External Memories
  • 36 DDR-SDRAM Controller (MPDDRC)
  • 37 Static Memory Controller (SMC)
  • 38 DMA Controller (XDMAC)
  • 39 LCD Controller (LCDC)
  • 40 Ethernet MAC (GMAC)
  • 41 USB Device High Speed Port (UDPHS)
  • 42 USB Host High Speed Port (UHPHS)
  • 43 Audio Class D Amplifier (CLASSD)
  • 44 Inter-IC Sound Controller (I2SC)
  • 45 Synchronous Serial Controller (SSC)
  • 46 Two-wire Interface (TWIHS)
  • 47 Flexible Serial Communication Controller (FLEXCOM)
  • 48 Universal Asynchronous Receiver Transmitter (UART)
  • 49 Serial Peripheral Interface (SPI)
  • 50 Quad Serial Peripheral Interface (QSPI)
  • 51 Secure Digital MultiMedia Card Controller (SDMMC)
  • 52 Image Sensor Controller (ISC)
  • 53 Controller Area Network (MCAN)
  • 54 Timer Counter (TC)
  • 55 Pulse Density Modulation Interface Controller (PDMIC)
  • 56 Pulse Width Modulation Controller (PWM)
  • 57 Secure Fuse Controller (SFC)
  • 58 Integrity Check Monitor (ICM)
  • 59 Advanced Encryption Standard Bridge (AESB)
  • 60 Advanced Encryption Standard (AES)
  • 61 Secure Hash Algorithm (SHA)
  • 62 Triple Data Encryption Standard (TDES)
  • 63 True Random Number Generator (TRNG)
  • 64 Analog Comparator Controller (ACC)
  • 65 Security Module (SECUMOD)
  • 66 Analog-to-Digital Controller (ADC)
  • 67 Electrical Characteristics
  • 68 Mechanical Characteristics
  • 69 Marking
  • 70 Ordering Information
  • 71 Revision History
  • Microchip Information

34.5.15.2 Software Freeze

Once the I/O line configuration is done, it can be frozen by using the PIO I/O Freeze Configuration Register (PIO_IOFRx) of the corresponding group or the Secure PIO I/O Freeze Configuration Register (S_PIO_IOFRx) if the I/O line is Secure.

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