49.8.13 SPI FIFO Mode Register
| Name: | SPI_FMR |
| Offset: | 0x40 |
| Reset: | 0x0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RXFTHRES[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXFTHRES[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXRDYM[1:0] | TXRDYM[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 29:24 – RXFTHRES[5:0] Receive FIFO Threshold
| Value | Description |
|---|---|
| 0–16 |
Defines the Receive FIFO threshold value (number of data). SPI_SR.RXFTH will be set when the Receive FIFO goes from “below” threshold state to “equal or above” threshold state. |
Bits 21:16 – TXFTHRES[5:0] Transmit FIFO Threshold
| Value | Description |
|---|---|
| 0–16 |
Defines the Transmit FIFO threshold value (number of data). SPI_SR.TXFTH will be set when the Transmit FIFO goes from “above” threshold state to “equal or below” threshold state. |
Bits 5:4 – RXRDYM[1:0] Receive Data Register Full Mode
If FIFOs are enabled, the SPI_SR.RDRF flag behaves as follows:
| Value | Name | Description |
|---|---|---|
| 0 | ONE_DATA |
RDRF will be at level ‘1’ when at least one unread data is in the Receive FIFO. |
| 1 | TWO_DATA |
RDRF will be at level ‘1’ when at least two unread data are in the Receive FIFO. Cannot be used when SPI_MR.MSTR =1, or if SPI_MR.PS =1. |
| 2 | FOUR_DATA |
RDRF will be at level ‘1’ when at least four unread data are in the Receive FIFO. Cannot be used when SPI_CSRx.BITS is greater than 0, or if SPI_MR.MSTR =1, or if SPI_MR.PS =1. |
Bits 1:0 – TXRDYM[1:0] Transmit Data Register Empty Mode
If FIFOs are enabled, the SPI_SR.TDRE flag behaves as follows:
| Value | Name | Description |
|---|---|---|
| 0 | ONE_DATA |
TDRE will be at level ‘1’ when at least one data can be written in the Transmit FIFO. |
| 1 | TWO_DATA |
TDRE will be at level ‘1’ when at least two data can be written in the Transmit FIFO. Cannot be used if SPI_MR.PS =1. |