24.4.3.1 General Reset

A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Start-up Counter. The purpose of this counter is to make sure the slow RC oscillator is stable before starting up the device. The oscillator start-up time is hard-coded.

After start-up, the processor clock is released at fast RC oscillator clock and all the other signals remain valid for two cycles for proper processor and logic reset. Then, all the reset signals are released and RSTC_SR.RSTTYP reports a general reset.

When VDDBU is detected low by the backup supply POR cell, all resets signals are immediately asserted, even if the main supply POR cell does not report a main supply shutdown.

VDDBU only activates the backup reset signal.

Backup reset must be released so that any other reset can be generated by VDDCORE (main supply POR output).

The figure below shows how the general reset affects the reset signals.