28.8.5 Control B

Name: CTRLB
Offset: 0x04
Reset: 0x0000
Property: Write-Protected, Write-Synchronized

Bit 15141312111098 
      PRESCALER[2:0] 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
   RESSEL[1:0]CORRENFREERUNLEFTADJDIFFMODE 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 10:8 – PRESCALER[2:0] Prescaler Configuration

These bits define the ADC clock relative to the peripheral clock.

PRESCALER[2:0]NameDescription
0x0DIV4Peripheral clock divided by 4
0x1DIV8Peripheral clock divided by 8
0x2DIV16Peripheral clock divided by 16
0x3DIV32Peripheral clock divided by 32
0x4DIV64Peripheral clock divided by 64
0x5DIV128Peripheral clock divided by 128
0x6DIV256Peripheral clock divided by 256
0x7DIV512Peripheral clock divided by 512

Bits 5:4 – RESSEL[1:0] Conversion Result Resolution

These bits define whether the ADC completes the conversion at 12-, 10- or 8-bit result resolution.

RESSEL[1:0]NameDescription
0x012BIT12-bit result
0x116BITFor averaging mode output
0x210BIT10-bit result
0x38BIT8-bit result

Bit 3 – CORREN Digital Correction Logic Enabled

ValueDescription
0

Disable the digital result correction.

1

Enable the digital result correction. The ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. Conversion time will be increased by X cycles according to the value in the Offset Correction Value bit group in the Offset Correction register.

Bit 2 – FREERUN Free Running Mode

ValueDescription
0

The ADC run is single conversion mode.

1

The ADC is in free running mode and a new conversion will be initiated when a previous conversion completes.

Bit 1 – LEFTADJ Left-Adjusted Result

ValueDescription
0

The ADC conversion result is right-adjusted in the RESULT register.

1

The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. Writing this bit to zero (default) will right-adjust the value in the RESULT register.

Bit 0 – DIFFMODE Differential Mode

ValueDescription
0

The ADC is running in singled-ended mode.

1

The ADC is running in differential mode. In this mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC.