27.10.9 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x0D
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
   MC1MC0SYNCRDY ERROVF 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 4, 5 – MCx Match or Capture Channel x Interrupt Enable [x = 1..0]

Writing a '0' to these bits has no effect.

Writing a '1' to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the Match or Capture Channel x interrupt.

ValueDescription
0 The Match or Capture Channel x interrupt is disabled.
1 The Match or Capture Channel x interrupt is enabled.

Bit 3 – SYNCRDY Synchronization Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the Synchronization Ready interrupt.

ValueDescription
0 The Synchronization Ready interrupt is disabled.
1 The Synchronization Ready interrupt is enabled.

Bit 1 – ERR Error Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.

ValueDescription
0 The Error interrupt is disabled.
1 The Error interrupt is enabled.

Bit 0 – OVF Overflow Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request.

ValueDescription
0 The Overflow interrupt is disabled.
1 The Overflow interrupt is enabled.