14.8.5 Generic Clock Generator Division
| Name: | GENDIV |
| Offset: | 0x8 |
| Reset: | 0x00000000 |
| Property: | Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DIV[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ID[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 23:8 – DIV[15:0] Division Factor
These bits apply a division on each selected generic clock generator. The number of DIV bits each generator has can be seen in the table below. Writes to bits above the specified number will be ignored.
| Generator | Division Factor Bits | Maximum Division Factor |
|---|---|---|
| Generic clock generator 0 | 8 division factor bits - DIV[7:0] | 512 |
| Generic clock generator 1 | 16 division factor bits - DIV[15:0] | 131072 |
| Generic clock generators 2 | 5 division factor bits - DIV[4:0] | 64 |
| Generic clock generators 3-8 | 8 division factor bits - DIV[7:0] | 512 |
Bits 3:0 – ID[3:0] Generic Clock Generator Selection
These bits select the generic clock generator on which the division factor will be applied, as shown in the table below.
| Values | Description |
|---|---|
| 0x0 | Generic clock generator 0 |
| 0x1 | Generic clock generator 1 |
| 0x2 | Generic clock generator 2 |
| 0x3 | Generic clock generator 3 |
| 0x4 | Generic clock generator 4 |
| 0x5 | Generic clock generator 5 |
| 0x6 | Generic clock generator 6 |
| 0x7 | Generic clock generator 7 |
| 0x8-0xF | Reserved |
A power reset will reset the GENDIV register for all IDs, including the generic clock generator used by the RTC. If a generic clock generator ID, other than generic clock generator ‘0’, is not a source of locked generic clock or a source of the RTC generic clock. A user reset will reset the GENDIV register for this ID. After a power reset, the reset value of the GENDIV register is as shown in the table below.
| GCLK Generator ID | Reset Value after a Power Reset |
|---|---|
| 0x00 | 0x00000000 |
| 0x01 | 0x00000001 |
| 0x02 | 0x00000002 |
| 0x03 | 0x00000003 |
| 0x04 | 0x00000004 |
| 0x05 | 0x00000005 |
| 0x06 | 0x00000006 |
| 0x07 | 0x00000007 |
After a user reset, the reset value of the GENDIV register is as shown in the table below.
| GCLK Generator ID | Reset Value after a User Reset |
|---|---|
| 0x00 | 0x00000000 |
| 0x01 | 0x00000001, if the generator is not used by the RTC and not a source of locked generic clock . No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one. |
| 0x02 | 0x00000002, if the generator is not used by the RTC and not a source of locked generic clock. No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one. |
| 0x03 | 0x00000003, if the generator is not used by the RTC and not a source of locked generic clock . No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one. |
| 0x04 | 0x00000004, if the generator is not used by the RTC and not a source of locked generic clock . No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one. |
| 0x05 | 0x00000005, if the generator is not used by the RTC and not a source of locked generic clock . No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one. |
| 0x06 | 0x00000006, if the generator is not used by the RTC and not a source of locked generic clock . No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one. |
| 0x07 | 0x00000007, if the generator is not used by the RTC and not a source of locked generic clock . No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one. |