23.5.1 PMD1 - Peripheral Module Disable 1 Register
Note: This register’s bits are only writable when
CFGCON0.PMDLOCK =
0.| Name: | PMD1 |
| Offset: | 0x00C0 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| QSPIMD | |||||||||
| Access | R/W/L | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CVDMD | ADCSARMD | ||||||||
| Access | R/W/L | R/W/L | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADCMD | ACMD | ||||||||
| Access | R/W/L | R/W/L | |||||||
| Reset | 0 | 0 |
Bit 29 – QSPIMD QSPI Module Disable
| Value | Description |
|---|---|
| 1 | Disables the QSPI module |
| 0 | Enables the QSPI module |
Bit 9 – CVDMD Shared CVD Module Disable Bit
| Value | Description |
|---|---|
| 1 | Disables the corresponding shared CVD module |
| 0 | Enables the corresponding shared CVD module |
Bit 8 – ADCSARMD Shared ADC SAR Core Module Disable Bit
| Value | Description |
|---|---|
| 1 | Disables the shared ADC SAR Core module |
| 0 | Enables the shared ADC SAR Core module |
Bit 7 – ADCMD ADC Controller Module Disable
| Value | Description |
|---|---|
| 1 | Disables the ADC Controller module |
| 0 | Enables the ADC Controller module |
Bit 6 – ACMD AC Module Disable
Note: PMD1.ACMD is not available in the
32-pin variant PIC32CX5109BZ31032/PIC32CX5109BZ36032 device.
| Value | Description |
|---|---|
| 1 | Disables the AC module |
| 0 | Enables the AC module |