3.3.15 SERCOM Inter-Integrated Circuit (SERCOM I2C) Electrical Specifications

Figure 3-6. I2C Start/Stop Bits Host Mode Timing Diagrams
Figure 3-7. I2C Bus Data Host Mode Timing Diagrams
Table 3-26. I2C Host Mode Electrical Specifications
Standard Operating Conditions: VDDIO = AVDD = 1.8V to 5.5V (unless otherwise stated)

Operating Temperature: -40°C ≤ TA ≤ +125°C for extended temperature

Param. No.SymbolCharacteristics(1)Min.Max.UnitsConditions
I2CM_1tL0:SCLHost Clock Low Time100 kHz mode4.7—µsVDD = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode1.3—µs
1 MHz mode0.5—µsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode320—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode160—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CM_3tHI:SCLHost Clock High Time100 kHz mode4—µsVDD = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode0.6—µs
1 MHz mode0.26—µsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode120—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode60—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CM_5tF:SCLSDAx and SCLx Fall Time100 kHz mode—300nsVDD = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode—300ns
1 MHz mode—120nsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode—80nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode—40nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CM_7tR:SCLSDAx and SCLx Rise Time100 kHz mode—1000nsVDD = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode—300ns
1 MHz mode—120nsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode—80nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode—40nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CM_9tSU:DATData Setup Time100 kHz mode250—nsVDD = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode100—ns
1 MHz mode50—nsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode10—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode10—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CM_11tHD:DAT(1)Data Hold Time100 kHz mode300—nsVDD = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode300—ns
1 MHz mode300—nsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode5—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode5—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CM_13tSU:STAStart Condition Setup Time100 kHz mode4.7—µsVDD= 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode0.6—µs
1 MHz mode0.26—µsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode160—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode160—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CM_15tHD:STAStart Condition Hold Time100 kHz mode4—µsVDD = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode0.6—µs
1 MHz mode0.26—µsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode160—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode160—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CM_17tSU:ST0Stop Condition Setup Time100 kHz mode4—µsVDD = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode0.6—µs
1 MHz mode0.26—µsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode160—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode160—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CM_21tAA:SCLOutput Valid from Clock100 kHz mode—3.45µsVDD = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode—0.9µs
1 MHz mode—0.45µsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode—100nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode—100nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CM_23tBF:SDA(2)Bus Free Time 100 kHz mode4.7—µsVDD = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode1.3—µs
1 MHz mode0.5—µsVDD = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode320—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode160—nsVDD = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

Note:
  1. The longest delay between data hold timing is based on the SDAHOLD bit field of the CTRLA register from the SERCOM module and the timing based on four periods of GCLKSERCOM for 100 kHz, 400 kHz and 1 MHz modes.
  2. The amount of time the bus must be free before a new transmission starts (from STOP condition to START condition).
Figure 3-8. I2C Start/Stop Bits Client Mode Timing Diagram
Figure 3-9. I2C Bus Data Client Mode Timing Diagrams
Table 3-27. I2C Client Mode AC Electrical Specifications
Standard Operating Conditions: VDD = AVDD = 1.8V to 5.5V (unless otherwise stated)

Operating Temperature: -40°C ≤ TA ≤ +125°C for extended temperature

Param. No.SymbolCharacteristics(1)Min.Max.UnitsConditions
I2CS_1tL0:SCLHost Clock Low Time100 kHz mode4.7—µsVDDIO = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode1.3—µs
1 MHz mode0.5—µsVDDIO = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz320—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode160—nsVDDIO= 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CS_3tHI:SCLHost Clock High Time100 kHz mode4.0—µsVDDIO = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode0.6—µs
1 MHz mode0.26—µsVDDIO = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode120—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode60—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CS_5tF:SCLSDAx and SCLx Fall Time100 kHz mode—300nsVDDIO = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode—300ns
1 MHz mode—120nsVDDIO = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz—80nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode—40nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CS_7tR:SCLSDAx and SCLx Rise Time100 kHz mode—1000nsVDDIO = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode—300ns
1 MHz mode—120nsVDDIO = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz—80nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode—40nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CS_9tSU:DATData Setup Time100 kHz mode250—nsVDDIO = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode100—ns
1 MHz mode50—nsVDDIO = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz10—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode10—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CS_11tHD:DAT(1)Data Hold Time100 kHz mode300—nsVDDIO = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode300—ns
1 MHz mode300—nsVDDIO = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz5—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode5—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CS_13tSU:STAStart Condition Setup Time100 kHz mode4.7—µsVDDIO = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode0.6—µs
1 MHz mode0.26—µsVDDIO = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode160—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode160—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CS_15tHD:STAStart Condition Hold Time100 kHz mode4.0—µsVDDIO = 5.0V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode0.6—µs
1 MHz mode0.26—µsVDDIO = 5.0V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode160—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode160—nsVDDIO = 5.0V, IPULL-UP = 20 mA,

CLOAD = 100 pF

I2CS_17tSU:ST0Stop Condition Setup Time100 kHz mode4.0—µsVDDIO = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode0.6—µs
1 MHz mode0.26—µsVDDIO = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz160—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode160—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CS_21tAA:SCLOutput Valid from Clock100 kHz mode—3.45µsVDDIO = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode—0.9µs
1 MHz mode—0.45µsVDDIO = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode—100nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode—100nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

I2CS_23tBF:SDA(2)Bus Free Time 100 kHz mode4.7—µsVDDIO = 3.3V, IPULL-UP = 3 mA,

CLOAD = 400 pF

400 kHz mode1.3—µs
1 MHz mode0.5—µsVDDIO = 3.3V, IPULL-UP = 20 mA,

CLOAD = 550 pF

1.7 MHz mode320—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 400 pF

3.4 MHz mode160—nsVDDIO = 3.3V, IPULL-UP = 12 mA,

CLOAD = 100 pF

Note:
  1. The longest delay between data hold timing is based on the SDAHOLD bit field of the CTRLA register from the SERCOM module and the timing based on four periods of GCLKSERCOM for 100 kHz, 400 kHz and 1 MHz modes.
  2. The amount of time the bus must be free before a new transmission starts (from STOP condition to START condition).