41.4.1 External Clock/Oscillator Timing Requirements

Figure 41-4. Clock Timing
Table 41-7. 
Standard Operating Conditions (unless otherwise stated)
Param. No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
ECL Oscillator
OS1FECLClock Frequency1MHz
OS2TECL_DCClock Duty Cycle4060%
ECH Oscillator
OS5FECHClock Frequency32MHzVDD ≥ 2.7V
16MHzVDD < 2.7V
OS6TECH_DCClock Duty Cycle4060%
Secondary Oscillator
OS10FSECClock Frequency32.768kHz(Note 4)
System Oscillator
OS20FOSCSystem Clock Frequency32MHz(Note 2, Note 3)
OS21FCYInstruction FrequencyFOSC/4MHz
OS22TCYInstruction Period1251/FCYns
Note:
  1. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
  2. The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in the “Power Saving Operation Modes” section.
  3. The system clock frequency (FOSC) must meet the voltage requirements defined in the “Standard Operating Conditions” section.