41.4.7 Analog-to-Digital Converter (ADC) Conversion Timing Specifications

Table 41-13.
Standard Operating Conditions (unless otherwise stated)
Param. No.	Sym.	Characteristic	Min.	Typ. †	Max.	Units	Conditions
AD20	T_AD	ADC Clock Period	—	—	—	μs	Using F_OSC as the ADC clock source ADOCS = `0`
AD20	T_AD	ADC Clock Period	—	2	—	μs	Using ADCRC as the ADC clock source ADOCS = `1`
AD21	T_CNV	Conversion Time	—	14 T_AD+2T_CY	—	—	Using F_OSC as the ADC clock source ADOCS = `0`
AD21	T_CNV	Conversion Time	—	16 T_AD+2T_CY	—	—	Using ADCRC as the ADC clock source ADOCS = `1`
AD22	T_HCD	Sample-and-Hold Capacitor Disconnect Time	—	2 T_AD+1T_CY	—	—	Using F_OSC as the ADC clock source ADOCS = `0`
AD22	T_HCD	Sample-and-Hold Capacitor Disconnect Time	—	3 T_AD+2T_CY	—	—	Using ADCRC as the ADC clock source ADOCS = `1`
* These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Figure 41-10. ADC Conversion Timing (ADC Clock F_OSC-Based)

Figure 41-11. ADC Conversion Timing (ADC Clock from ADCRC)

Note:

If the ADC clock source is selected as ADCRC, a time of T_CY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.