12.10.6 PIE4
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt controlled by registers PIE1 through PIE4.
| Name: | PIE4 |
| Offset: | 0x009A |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ZCDIE | ADTIE | ADIE | CM1IE | BCL2IE | SSP2IE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – ZCDIE Zero-Cross Detect (ZCD) Interrupt Enable
| Value | Description |
|---|---|
| 1 | ZCD interrupts are enabled |
| 0 | ZCD interrupts are disabled |
Bit 4 – ADTIE ADC Threshold Interrupt Enable
| Value | Description |
|---|---|
| 1 | ADC Threshold interrupts are enabled |
| 0 | ADC Threshold interrupts are disabled |
Bit 3 – ADIE ADC Interrupt Enable
| Value | Description |
|---|---|
| 1 | ADC interrupts are enabled |
| 0 | ADC interrupts are disabled |
Bit 2 – CM1IE Comparator 1 Interrupt Enable
| Value | Description |
|---|---|
| 1 | Comparator 1 interrupts are enabled |
| 0 | Comparator 1 interrupts are disabled |
Bit 1 – BCL2IE MSSP2 Bus Collision Interrupt Enable
| Value | Description |
|---|---|
| 1 | MSSP2 Bus Collision interrupts are enabled |
| 0 | MSSP2 Bus Collision interrupts are disabled |
Bit 0 – SSP2IE MSSP2 Interrupt Enable
| Value | Description |
|---|---|
| 1 | MSSP2 interrupts are enabled |
| 0 | MSSP2 interrupts are disabled |