12.10.8 PIR1

Peripheral Interrupt Request Register 1
Note:
  1. Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name: PIR1
Offset: 0x008D

Bit 76543210 
 TMR2IFTMR3GIFTMR3IFTMR1GIFTMR1IFACTIF NVMIF 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 0000000 

Bit 7 – TMR2IF TMR2 Interrupt Flag

ValueDescription
1 TMR2 interrupt has occurred (must be cleared in software)
0 TMR2 interrupt event has not occurred

Bit 6 – TMR3GIF TMR3 Gate Interrupt Flag

ValueDescription
1 The TMR3 Gate has gone inactive (must be cleared in software)
0 TMR3 Gate is active

Bit 5 – TMR3IF TMR3 Interrupt Flag

ValueDescription
1 TMR3 interrupt has occurred (must be cleared in software)
0 TMR3 interrupt event has not occurred

Bit 4 – TMR1GIF TMR1 Gate Interrupt Flag

ValueDescription
1 The TMR1 Gate has gone inactive (must be cleared in software)
0 TMR1 Gate is active

Bit 3 – TMR1IF TMR1 Interrupt Flag

ValueDescription
1 TMR1 interrupt has occurred (must be cleared in software)
0 TMR1 interrupt event has not occurred

Bit 2 – ACTIF Active Clock Tuning Interrupt Flag

ValueDescription
1 Active Clock Tuning interrupt occurred (must be cleared in software)
0 Active Clock Tuning interrupt event has not occurred

Bit 0 – NVMIF Nonvolatile Memory (NVM) Interrupt Flag

ValueDescription
1 The requested NVM operation has completed (must be cleared in software)
0 NVM interrupt event has not occurred
Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.