12.10.5 PIE3
Note:
- Bit PEIE in the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1 through PIE4.
| Name: | PIE3 |
| Offset: | 0x0099 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BCL1IE | SSP1IE | RC2IE | TX2IE | RC1IE | TX1IE | CLC4IE | CLC3IE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – BCL1IE MSSP1 Bus Collision Interrupt Enable
| Value | Description |
|---|---|
| 1 | MSSP1 Bus Collision interrupts are enabled |
| 0 | MSSP1 Bus Collision interrupts are disabled |
Bit 6 – SSP1IE MSSP1 Interrupt Enable
| Value | Description |
|---|---|
| 1 | MSSP1 interrupts are enabled |
| 0 | MSSP1 interrupts are disabled |
Bit 5 – RC2IE EUSART2 Receive Interrupt Enable
| Value | Description |
|---|---|
| 1 | EUSART2 receive interrupts are enabled |
| 0 | EUSART2 receive interrupts are disabled |
Bit 4 – TX2IE PWM1 Period Interrupt Enable
| Value | Description |
|---|---|
| 1 | EUSART2 transmit interrupts are enabled |
| 0 | EUSART2 transmit interrupts are disabled |
Bit 3 – RC1IE EUSART1 Receive Interrupt Enable
| Value | Description |
|---|---|
| 1 | EUSART1 receive interrupts are enabled |
| 0 | EUSART1 receive interrupts are disabled |
Bit 2 – TX1IE EUSART1 Transmit Interrupt Enable
| Value | Description |
|---|---|
| 1 | EUSART1 transmit interrupts are enabled |
| 0 | EUSART1 transmit interrupts are disabled |
Bit 1 – CLC4IE CLC4 Interrupt Enable
| Value | Description |
|---|---|
| 1 | CLC4 interrupts are enabled |
| 0 | CLC4 interrupts are disabled |
Bit 0 – CLC3IE CLC3 Interrupt Enable
| Value | Description |
|---|---|
| 1 | CLC3 interrupts are enabled |
| 0 | CLC3 interrupts are disabled |