12.10.4 PIE2
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt controlled by registers PIE1 through PIE4.
| Name: | PIE2 |
| Offset: | 0x0098 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLC2IE | CLC1IE | CWG1IE | NCO1IE | CCP2IE | CCP1IE | TMR6IE | TMR4IE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – CLC2IE CLC2 Interrupt Enable
| Value | Description |
|---|---|
| 1 | CLC2 interrupts are enabled |
| 0 | CLC2 interrupts are disabled |
Bit 6 – CLC1IE CLC1 Interrupt Enable
| Value | Description |
|---|---|
| 1 | CLC1 interrupts are enabled |
| 0 | CLC1 interrupts are disabled |
Bit 5 – CWG1IE CWG1 Interrupt Enable
| Value | Description |
|---|---|
| 1 | CWG1 interrupts are enabled |
| 0 | CWG1 interrupts are disabled |
Bit 4 – NCO1IE NCO1 Interrupt Enable
| Value | Description |
|---|---|
| 1 | NCO1 interrupts are enabled |
| 0 | NCO1 interrupts are disabled |
Bit 3 – CCP2IE CCP2 Interrupt Enable
| Value | Description |
|---|---|
| 1 | CCP2 interrupts are enabled |
| 0 | CCP2 interrupts are disabled |
Bit 2 – CCP1IE CCP1 Interrupt Enable
| Value | Description |
|---|---|
| 1 | CCP1 interrupts are enabled |
| 0 | CCP1 interrupts are disabled |
Bit 1 – TMR6IE TMR6 Interrupt Enable
| Value | Description |
|---|---|
| 1 | TMR6 interrupts are enabled |
| 0 | TMR6 interrupts are disabled |
Bit 0 – TMR4IE TMR4 Interrupt Enable
| Value | Description |
|---|---|
| 1 | TMR4 interrupts are enabled |
| 0 | TMR4 interrupts are disabled |