31.5.5 ADSTAT
Note:
- MATH bit cannot be cleared by
software while STAT =
‘b100. - If ADC clock source is ADCRC, and FOSC < ADCRC, the indicated status may not be valid.
- STAT =
‘b100appears between the two triggers when DSEN =1and CONT =0.
| Name: | ADSTAT |
| Offset: | 0x1D2A |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| AOV | UTHR | LTHR | MATH | STAT[2:0] | |||||
| Access | R/C/HS/HC | R | R | R/W/HS | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – AOV ADC Accumulator Overflow
| Value | Description |
|---|---|
| 1 | ADACC or ADFLTR or ADERR registers have overflowed |
| 0 | ADACC, ADFLTR and ADERR registers have not overflowed |
Bit 6 – UTHR ADC Module Greater-than Upper Threshold Flag
| Value | Description |
|---|---|
| 1 | ADERR > ADUTH |
| 0 | ADERR ≤ ADUTH |
Bit 5 – LTHR ADC Module Less-than Lower Threshold Flag
| Value | Description |
|---|---|
| 1 | ADERR < ADLTH |
| 0 | ADERR ≥ ADLTH |
Bit 4 – MATH ADC Module Computation Status
ADC Module Computation Status(1)
| Value | Description |
|---|---|
| 1 | Registers ADACC, ADFLTR, ADUTH, ADLTH and the AOV bit are updating or have already updated |
| 0 | Associated registers/bits have not changed since this bit was last cleared |
Bits 2:0 – STAT[2:0] ADC Module Cycle Multi-Stage Status
| Value | Description |
|---|---|
| 111 | ADC module is in 2nd conversion stage |
| 110 | ADC module is in 2nd acquisition stage |
| 101 | ADC module is in 2nd precharge stage |
| 100 | ADC computation is suspended between 1st and 2nd sample; the computation results are incomplete and awaiting data from the 2nd sample(2,3) |
| 011 | ADC module is in 1st conversion stage |
| 010 | ADC module is in 1st acquisition stage |
| 001 | ADC module is in 1st precharge stage |
| 000 | ADC module is not converting |