17.3.11 PORTWCLK

Signal Routing Port Clock Selection
Note: This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock for details.
Name: PORTWCLK
Offset: 0x1F2C

Bit 76543210 
    CLK[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 4:0 – CLK[4:0]  Signal Routing Port Clock Input Selection

Table 17-2. Signal Routing Port Clock Input Selections
ValueDescription
11111-11000Reserved
10111NCO1_OUT
10110CLC4_OUT
10101CLC3_OUT
10100CLC2_OUT
10011CLC1_OUT
10010PWM2S1P2_OUT
10001PWM2S1P1_OUT
10000PWM1S1P2_OUT
01111PWM1S1P1_OUT
01110CCP2_OUT
01101CCP1_OUT
01100TMR1_overflow
01011TMR0_overflow
01010TMR4_OUT
01001TMR2_OUT
01000CLKREF_OUT
00111EXTOSC
00110SOSC
00101MFINTOSC (31.25 kHz)
00100MFINTOSC (500 kHz)
00011LFINTOSC
00010HFINTOSC
00001FOSC
00000PORTWCLKPPS
Reset States: 
POR/BOR = 00000
All Other Resets = 00000
This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock for details.