17.1.1 Signal Routing Port Clock

The PORTWCLK register offers an extensive selection of clock sources for the Signal Routing Port module. This acts as a clock input to the PORTW data register, allowing for the formation of hardware-based state machines and delay operations. All the pins in a Signal Routing Port are clocked using this common clock. If a device has multiple Signal Routing Ports, each Signal Routing Port has its own clock input and control. Clock polarity can be selected using the PORTW Clock Polarity (CPOL) bit.

The PORTWCON register contains the clock enable bits for all Signal Routing Ports on the device. The CLKEN bit enables/disables the module clock and synchronizers. When CLKEN = 0, the module clock to the PORTW data register is disabled and all Signal Routing Port SFRs can be written and read from. When CLKEN = 1, the PORTW data register is clocked as per the PORTWCLK selection. Only LATW register has read/write access, all other registers are read-only when the clock is enabled.

CAUTION: When the user writes '1' to the CLKEN bit to enable the module clock, the data flops are immediately loaded with the corresponding input signals as selected using the PORTWINx registers.