39.2 Comparator Control

Each comparator has two control registers: CMLPxCON0 and CMLPxCON1.

The CMLPxCON0 register contains control bits for the following:

  • Enable
  • Output
  • Output Polarity
  • Timer1 Output Synchronization

The CMLPxCON1 register contains control bits for the following:

  • Input common-mode range selection
  • Interrupt on Positive/Negative Edge enables

The CMLPxPCH and CMLPxNCH registers are used to select the positive and negative input channels, respectively.