37.17 ADC
Operating Conditions:
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|---|---|---|---|---|---|---|
| Symbol | Description | Min. | Typ. ✝ | Max. | Unit | Conditions |
| NR | Resolution | — | — | 12 | bit | |
| EINL | Integral nonlinearity error | -1.5 | 0.1 | 1.5 | LSb | VDD=VREF=3.0V |
| EDNL | Differential nonlinearity error(1) | -1 | 0.1 | 1 | LSb | VDD=VREF=3.0V |
| EOFF | Offset error | -5 | 2.5 | 5 | LSb | VDD=VREF=3.0V |
| EGAIN | Gain error | -5 | 1.5 | 5 | LSb | VDD=VREF=3.0V |
| EABS | Absolute error | — | — | — | LSb | VDD=VREF=3.0V |
| VADCREF | ADC reference voltage | 1.8 | — | VDD | V | |
| VAIN | Full-scale range | GND | — | VADCREF | V | |
| ZAIN | Recommended impedance of analog voltage source | — | 1 | — | kΩ | |
| RVREFA | ADC voltage reference ladder impedance(2) | — | 50 | — | kΩ | |
|
✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested. Note:
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| Symbol | Description | Min. | Typ. ✝ | Max. | Unit | Conditions |
|---|---|---|---|---|---|---|
| TCLK_ADC * | ADC clock period | 0.5 | — | 8 | μs | |
| tCNV | Conversion time | — | 13.5TCLK_ADC + 2TCLK_PER | — | ||
| tACQ | Acquisition time | — | 2TCLK_ADC | — | μs | |
| fADC * | Sample rate | 8 | — | 130 | ksps | |
| tS | Sampling time | — | 2TCLK_ADC | — | ||
| tSENSE * | Delay for changing MUXPOS to TEMP | — | 40 | — | μs | |
| tADC_INIT * | Initialization time | — | 6 | — | μs | |
|
✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested. * These parameters are characterized but not tested in production. | ||||||
