24.13.12 Periodic Interrupt Timer Control A
Important: Due to the
synchronization between the RTC clock and main clock domains, there is a latency of
two RTC clock cycles from updating the register until this has an effect. The
application software must check that the CTRLBUSY flag in the RTC.PITSTATUS register
is cleared before writing to this register.
Name: | PITCTRLA |
Offset: | 0x10 |
Reset: | 0x00 |
Property: | - |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PERIOD[3:0] | PITEN | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bits 6:3 – PERIOD[3:0] Period
Value | Name | Description |
---|---|---|
0x0 | OFF | No interrupt |
0x1 | CYC4 | 4 cycles |
0x2 | CYC8 | 8 cycles |
0x3 | CYC16 | 16 cycles |
0x4 | CYC32 | 32 cycles |
0x5 | CYC64 | 64 cycles |
0x6 | CYC128 | 128 cycles |
0x7 | CYC256 | 256 cycles |
0x8 | CYC512 | 512 cycles |
0x9 | CYC1024 | 1024 cycles |
0xA | CYC2048 | 2048 cycles |
0xB | CYC4096 | 4096 cycles |
0xC | CYC8192 | 8192 cycles |
0xD | CYC16384 | 16384 cycles |
0xE | CYC32768 | 32768 cycles |
0xF | - | Reserved |
Bit 0 – PITEN Periodic Interrupt Timer Enable
Value | Description |
---|---|
0 | Periodic Interrupt Timer disabled |
1 | Periodic Interrupt Timer enabled |