Introduction

The PolarFire® Field Programmable Gate Array (FPGA) family includes multiple embedded low power and performance-optimized transceivers. Each transceiver has both Physical Medium Attachment (PMA), Protocol Physical Coding Sub-layer (PCS) logic interfaces to the FPGA fabric.

The transceiver has a multi-lane architecture with each lane natively supporting serial data transmission rates ranging from 250 Mbps to 12.7 Gbps.

At the receiver front end, Continuous Time Linear Equalization (CTLE) with optional auto calibration compensates the high-frequency losses to improve the received signal integrity. However, for lossy channels, the CTLE technique amplifies the high-frequency noise along with the data. This is resolved by using Decision Feedback Equalization (DFE), which mitigates lane noise caused due to Inter Symbol Interference (ISI) or crosstalk without amplifying the high-frequency noise within the data.

CTLE technique is sufficient to interpret data up to 8 Gbps for short reach applications. Beyond this, Decision Feedback Equalizer is capable of equalizing channel response. For more information on CTLE, DFE, and Transceiver insertion loss, see PolarFire FPGA and PolarFire SoC FPGA Transceiver User Guide.

An optionally enabled 5-tap DFE is available to equalize the lane response in conjunction with the CTLE.

The DFE-based operation uses current bit information to cancel ISI for the next bit through a feedback mechanism, allowing the next bits to be correctly sampled. Using taps to delay and by multiplying the symbols, the DFE effectively cancels out interference on the analog signal. The operation is nonlinear, allowing it to overcome the notch response that the CTLE does not perform. The DFE also includes an automatic calibration that finds the best possible tuning to match the transceiver lane to the system channel. DFE mode supports serial data transmission rates ranging from 3 Gbps to 12.7 Gbps.

Incremental DFE is another option of calibration to incrementally improve the performance of the DFE path.

Two independent algorithms, Data Eye Clock Centering Re-calibration and DFE Coefficient Re-calibration, offer incremental methods to improve DFE path performance after an initial calibration. These algorithms help in improving Data Eye for the most gradients, which occur from temperature and voltage and reduces the calibration time significantly. You can select the incremental DFE option in configurator, allowing them to trigger inputs for this calibration.

This application note demonstrates the simple procedure to perform run time DFE calibration using a Dynamic Reconfiguration Interface (DRI). It also shows how to plot eye diagrams using the SmartDebug tool and verify signal integrity in DFE mode. DFE equalization enables PolarFire transceivers to be efficient for systems running at approximately 10 Gbps or above where channel complexity is higher.