6 Running the Demo

This section describes how to optimize DFE coefficients and check the result on board.

Prerequisites for the procedure:

  • The PolarFire Evaluation board is connected.
  • The PolarFire FPGA is programmed with the DFE design.
To run the demo, perform the following steps:
  1. After the device is programmed, change SW11 DIP1 from 0 to 1. This brings the CoreABC interface out of reset and starts DFE calibration.
    Important: Trigger for DFE calibration is also generated by monitoring the condition (RX_READY and RX_IDLE).
  2. Observe if LED4 is OFF, and LED10 and LED5 are in ON state. This signifies that run time DFE calibration is complete and there is no bit error. Here LED4 represent bit error status, LED10 represent data lock flag signal, and LED5 represents DFE calibration status.

Eye Monitor enables visualizing the eye diagram present within the receiver. This feature plots the receive eye after the CTLE and DFE functions. For plotting the Eye Diagram, follow the following procedure.

On the Design Flow window, perform the following steps:
  1. To generate data for SmartDebug Design, click Generate SmartDebug FPGA Array Data. Once the data is generated, a green tick mark is seen on the left side of the option indicating that the data generation is successful.
  2. To open SmartDebug Design, double-click Debug Design.
    Figure 6-1. Launching SmartDebug Design
  3. Open the SmartDebug window, and then click Debug TRANSCEIVER as shown in following figure.
    Figure 6-2. SmartDebug Window Debug Options
  4. On EYE Monitor tab, select LANE0.
  5. To plot the eye, click Plot Eye.

The following figure shows the Eye Plot.

Figure 6-3. Eye Plot