4 Demo Design

The following sequence describes the data flow in the demo design and ensure that the transceiver CDR is locked:
  1. The design uses a transceiver interface (PF_XCVR) configured in native PMA mode running at 10.3125 Gbps data-rate, 40-bit PCS fabric interface, and using 125 MHz reference clock.
  2. The PRBS_Generator module generates a PRBS-7 pattern and forwards the data to the Transceiver Tx end.
  3. The differential serial data of Tx and Rx is looped back using the onboard SMA-to-SMA cables.
  4. This data is then received by the PRBS_checker module, which checks for data match. If matched the Lock is asserted, otherwise, an error signal is generated.
The following sequence describes how DFE calibration is triggered:
  1. When the CDR is locked, valid RX_IDLE and RX_READY signals are sent to the Flag_for_RXPLL_lock_0 module.
    Important: RX_IDLE is low during data transmission and RX_READY is asserted when CDR is locked to the incoming serial data.
  2. The Flag_for_RXPLL_lock_0 module determines proper transceiver RX PLL lock using the condition NOT RX_IDLE and RX_READY.
  3. When the preceding condition is true, Flag_0 is asserted and sent to the CoreABC module.
  4. This initiates the DFE calibration sequence using the CoreABC interface.
  5. CoreABC acts as APB3 master and dynamically performs Read/Write to transceiver registers using the PF_XCVR_DRI interface. The transceiver interface is connected as APB3 slave to the PF_XCVR_DRI interface.
  6. When the DFE calibration sequence is successful, the DFE_CAL_DONE flag is asserted.

The following figure shows the block diagram of the design.

Figure 4-1. DFE Block Diagram