| When DMA descriptor mode is enabled on either the source or the destination, but not
both, the DMA checks for address alignment against the transfer size of
the previously completed transfer rather than the current channel's
programmed transfer size in the descriptor. Consequently, if the
previous transfer used a 32-bit (word) size and the current transfer is
configured for 8-bit (byte), the DMA may incorrectly flag an Address
Alignment Error (ADRERR) and generate a bus trap if the address is not
word-aligned. |
| Workaround Enable descriptor mode on both the source and destination
sides (SDTEN = 1 and DDTEN = 1),
or ensure all DMA transfers use a 32-bit transfer size with
word-aligned addresses. |
| Affected Silicon Revisions |
