Introduction

The dsPIC33AK256MPS306 family devices that you have received conform functionally to the current device data sheet (DS70005629B), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table . The silicon issues are summarized in Table .

The errata described in this document will be addressed in future revisions of the dsPIC33AK256MPS306 family silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table apply to the current silicon revision (A0).

Data sheet clarifications and corrections start on Data Sheet Clarifications, following the discussion of silicon issues.

The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers and emulation tools, which are available at the Microchip corporate website (www.microchip.com).

To determine the silicon revision level using MPLAB IDE with a hardware debugger, follow these steps:

  1. Connect the device to the hardware debugger using the appropriate interface.
  2. Open an MPLAB IDE project.
  3. Configure the MPLAB IDE project for the correct device and hardware debugger.
  4. Perform one of the following actions, depending on your version of MPLAB IDE:
    • For MPLAB IDE 8, navigate to Programmer > Reconnect.
    • For MPLAB X IDE, navigate to Window > Dashboard, and then click the Refresh Debug Tool Status icon ( ).
  5. The part number and Device Revision ID value appear in the Output window, depending on the development tool used.
    Note: If you cannot retrieve the silicon revision level, contact your local Microchip sales office for support.

The following table lists the DEVREV values for the various silicon revisions of the dsPIC33AK256MPS306 family.

Table . Silicon DEVREV Values
Part NumberDevice ID (1)Revision ID for Silicon Revision (1)
A0
dsPIC33AK128MPS3030xB5140x0000
dsPIC33AK128MPS3050xB515
dsPIC33AK128MPS3060xB516
dsPIC33AK256MPS3030xB51C
dsPIC33AK256MPS3050xB51D
dsPIC33AK256MPS3060xB51E
dsPIC33AK128MPS1030xB504
dsPIC33AK128MPS1050xB505
dsPIC33AK128MPS1060xB506
dsPIC33AK256MPS1030xB50C
dsPIC33AK256MPS1050xB50D
dsPIC33AK256MPS1060xB50E
Note:
  1. Refer to the “dsPIC33AK256MPS306 Family Flash Programming Specification” for detailed information on Device and Revision IDs for your specific device.
Table . Silicon Issue Summary
ModuleFeatureItem NumberIssue SummaryAffected Revisions (1)
A0
PWMPCI1In Complementary Output mode, when PSYNC is enabled in PCI Edge Detect mode, PCI override can be applied twice. X
PWMADC Trigger Events2In LLC mode, when TRIGy is equal to EOC and with CAPTREN set, ADC triggers are not generated when the ADC trigger source is TRIGy.X
PWMOverride3When PWML is configured for active override, the PWM outputs are not overridden. X
I3C Controller,IBI4IBI data threshold (I3C1QUETHLDCON [IBIDATTHLD]) default value of 0 can cause the device to halt code execution.X
I3CTarget Mode5In Target mode, during data reception with DMA enabled, when the data buffer threshold I3C1BUFTHLD[RXTHLD] is configured greater than 0, data might be incorrectly stored in the RAM.X
PWRMModule Enable6The ON bit in VM1CON[31] will not enable the module.X
PWRMStatus Reporting7On device start up, the power monitor module can set the UVBG bit in the VM1EVENT[0] status bit erroneously.X
PWRMScan8If the power monitor is enabled during programming, the device ID might fail to be read. X
GPIOIO Current Limit9The source/sink capability of IO pins is less than the electrical specifications. X
CPUInterrupt Vectoring10Interrupt vectoring and simultaneous PBU/cache invalidation may stall the CPU indefinitely.X
SILICONSilicon Temperature Variants 11Silicon only supports Industrial temperature (-40°C to 85°C) and not Extended temperature (-40°C to 125°C). X
DMADescriptor Write-Back12With descriptor write-back enabled, the DMA always increments/decrements the payload pointer by 4 bytes, regardless of the descriptor’s configured element size.X
DMADescriptor Mode13If descriptor mode is enabled on only the source or only the destination, the DMA may use the previous transfer’s element size for alignment checking, potentially causing a false ADRERR/bus trap.X
Note:
  1. The issues shown in the last column apply specifically to the current silicon revision.