Introduction

The dsPIC33AK256MPS306 family devices that you have received conform functionally to the current device data sheet (DS70005629C), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table . The silicon issues are summarized in Table .

The errata described in this document will be addressed in future revisions of the dsPIC33AK256MPS306 family silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table apply to the current silicon revision (A1).

Data sheet clarifications and corrections start on Data Sheet Clarifications, following the discussion of silicon issues.

The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers and emulation tools, which are available at the Microchip corporate website (www.microchip.com).

To determine the silicon revision level using MPLAB IDE with a hardware debugger, follow these steps:

Connect the device to the hardware debugger using the appropriate interface.
Open an MPLAB^® X IDE project.
Configure the MPLAB X IDE project for the correct device and hardware debugger.
In MPLAB X IDE, navigate to Window > Dashboard, and then click the Refresh Debug Tool Status icon ( ).
The part number and Device Revision ID value appear in the Output window, depending on the development tool used.
Note: If you cannot retrieve the silicon revision level, contact your local Microchip sales office for support.

The following table lists the DEVREV values for the various silicon revisions of the dsPIC33AK256MPS306 family.

Table . Silicon DEVREV Values
Part Number	Device ID ⁽¹⁾	Revision ID for Silicon Revision ⁽¹⁾
Part Number	Device ID ⁽¹⁾	A0	A1
dsPIC33AK128MPS303	0xB514	0x0000	0x0001
dsPIC33AK128MPS305	0xB515
dsPIC33AK128MPS306	0xB516
dsPIC33AK256MPS303	0xB51C
dsPIC33AK256MPS305	0xB51D
dsPIC33AK256MPS306	0xB51E
dsPIC33AK128MPS103	0xB504
dsPIC33AK128MPS105	0xB505
dsPIC33AK128MPS106	0xB506
dsPIC33AK256MPS103	0xB50C
dsPIC33AK256MPS105	0xB50D
dsPIC33AK256MPS106	0xB50E
Note: Refer to the “dsPIC33AK256MPS306 Family Flash Programming Specification” for detailed information on Device and Revision IDs for your specific device.

Table . Silicon Issue Summary
Module	Feature	Item Number	Issue Summary	Affected Revisions ^(1,2)
Module	Feature	Item Number	Issue Summary	A0	A1
PWM	PCI	1	In Complementary Output mode, when PSYNC is enabled in PCI Edge Detect mode, PCI override can be applied twice.	X	X
PWM	ADC Trigger Events	2	In LLC mode, when TRIGy is equal to EOC and with CAPTREN set, ADC triggers are not generated when the ADC trigger source is TRIGy.	X	X
PWM	Override	3	When PWML is configured for active override, the PWM outputs are not overridden.	X	X
I3C	IBI Data Threshold	4	IBI data threshold (I3C1QUETHLDCON [IBIDATTHLD]) default value of `0` can cause the device to halt code execution.	X	X
I3C	Target Mode	5	In Target mode, during data reception with DMA enabled, when the data buffer threshold I3C1BUFTHLD[RXTHLD] is configured greater than `0`, data might be incorrectly stored in the RAM.	X	X
PWRM	Enable	6	The ON bit in VM1CON[31] will not enable the module.	X
PWRM	Event Status	7	On device start up, the power monitor module can set the UVBG bit in the VM1EVENT[0] status bit erroneously.	X
PWRM	Scan	8	If the power monitor is enabled during programming, the device ID might fail to be read.	X
GPIO	IO Current Limit	9	The source/sink capability of IO pins is less than the electrical specifications.	X
CPU	Interrupt Vector	10	Interrupt vectoring and simultaneous PBU/cache invalidation may stall the CPU indefinitely.	X	X
SILICON	Silicon Temperature Variants	11	Silicon only supports Industrial temperature (-40°C to 85°C) and not Extended temperature (-40°C to 125°C).	X
DMA	Descriptor Write-Back	12	With descriptor write-back enabled, the DMA always increments/decrements the payload pointer by 4 bytes, regardless of the descriptor’s configured element size.	X	X
DMA	Descriptor Mode	13	If descriptor mode is enabled on only the source or only the destination, the DMA may use the previous transfer’s element size for alignment checking, potentially causing a false ADRERR/bus trap.	X	X
SPI	Host Mode	14	SPI Host mode may exhibit unreliable operation when using peripheral bus clock.	X	X
In-Circuit Debugger	Breakpoints	15	If a hardware breakpoint is placed immediately after a conditional branch instruction, the breakpoint can be missed and will result in no debugger halt.	X	X
Note: Only the issues marked with an “X” in the last column apply to the current silicon revision. If the column cell is unmarked or blank, it indicates the issue is resolved in the latest revised silicon.