4.6.1 CLASSD I/O Pin Initialization

PIO pins PA28, PA29, PA30 and PA31 (for the left channel), and PB1, PB2, PB3 and PB4 (for the right channel), with peripheral function F, will be assigned to the CLASSD interface. The code snippet given below will initialize the I/O pins accordingly.

/* Set PORTA mask register bits 28, 29, 30 & 31 */
PIOA->PIO_IO_GROUP[0].PIO_MSKR = (0xF << 28);

/* Enable peripheral function F and set I/O pins as output */
PIOA->PIO_IO_GROUP[0].PIO_CFGR = PIO_CFGR_FUNC_PERIPH_F | PIO_CFGR_DIR_OUTPUT;

/* Set PORTB mask register bits 1, 2, 3 & 4 */
PIOA->PIO_IO_GROUP[1].PIO_MSKR = (0xF << 1);

/* Enable peripheral function F and set I/O pins as output */
PIOA->PIO_IO_GROUP[1].PIO_CFGR = PIO_CFGR_FUNC_PERIPH_F | PIO_CFGR_DIR_OUTPUT;