5.4 I2SC Clock Generator

The I2SC integrates a clock generator that generates the master clock (I2SMCK) and the bit clock (I2SCK) in Master mode and Controller mode.

The following figure shows the block diagram of the I2SC internal clock generator.

The input to the I2SC clock generator can be either the peripheral clock (MCK) or the generic clock (GCLK) from the power manager (PMC), which is selected by the bit CLKSELx in the matrix special function register SFR_I2SCLKSEL. The ‘x’ in CLKSELx stands for the I2SC instance number. The SAMA5D2 device has a maximum of two I2SC instances. One CLKSEL bit per instance is available. In Master mode, if the peripheral clock frequency is higher than 96 MHz, the GCLK clock from PMC must be selected as the I2SC input clock.

The I2SC master clock (I2SMCK) is derived from the selected clock. It has a master clock gate and a master clock divider in its path. The master clock gate enables/disables the I2SMCK, which is controlled by register bits I2SC_CR.CKEN/CKDIS and I2SC_MR.IMCKMODE, as shown in the figure. The master clock divider follows the master clock gate, which prescales the input clock by the division factor (I2SC_MR.IMCKDIV +1).

Assuming the I2SC master clock is 256*fs and the audio sample rate is 44.1 kHz, the I2SMCK obtained is 11.2896 MHz. The selected clock can be an integer multiple of I2SMCK. Assuming the selected clock is 4 times I2SMCK, the master clock division factor IMCKDIV should be 3. The power manager should be configured to generate a peripheral clock or a generic clock, which is 4 * 11.2896 MHz = 45.1584 MHz.

If the I2SC master clock is disabled (IMCKMODE = 0), the selected clock is taken as the I2SC bit clock (I2SCK). The I2SC bit clock path has a bit clock gate circuit, which is controlled by the I2SC_CR.CKEN/CKDIS bits.

If the I2SC master clock is enabled (IMCKMODE = 1), the clock output from the master clock gate is taken as the I2S bit clock with a bit clock divider included in the path. The bit clock divider is controlled by two parameters, namely I2SC_MR.IMCKFS and I2SC_MR.DATALENGTH, and its division factor is equal to (I2SC_MR.IMCKFS + 1).

Basically, the bit clock is defined by the following equation:

Bit clock = fs * no. of channels * no. of bits per channel

The number of bits per channel is the slot length. For the above example, fs = 44.1kHz, master clock = 256*fs, number of channels = 2, slot length = 16.

Bit clock = 44100 * 2 * 16 = 1.411200 MHz.

The bit clock divider should be configured to have a division factor of 32 (= 45.1584 MHz / 1.4112 MHz). This means that I2SC_MR.IMCKFS should be set to 31.

Note that the bit clock division factor is always equal to (fs * 2 * 16) regardless of the slot length. This means that even if the slot length is 32, the bit clock division factor is 1.411200 MHz for a sample rate of 44.1 kHz.

The word select clock signal is derived from the bit clock signal, and it has the word select clock divider in its path. The division factor of this clock divider is controlled by the DATALENGTH field such that the word select frequency is the same as the audio sample rate fs.

In Slave mode, the I2SCK pin acts as an input, and the bit clock is derived from this clock.