5.1 I2S Frame

The figure below depicts a standard I2S bus frame structure.

I2S transfers data synchronously based on the bit clock (I2SCK). Data bits are set up on the falling edge of the bit clock and sampled on the rising edge of the bit clock. The word select line (I2SWS) is used to identify which audio channel (left or right) the current data bits correspond to. Typically, the word select line is held low when transmitting left channel data and held high when transmitting right channel data.

As per the I2S protocol, data bits are left-justified with the MSB transmitted first, starting one bit clock period after the transition in the word select line.

An I2S bus typically includes one more clock line called the master clock line. The frequency of the master clock signal is a 2^x integer multiple of the audio sample rate fs, for example, 256*fs. This master clock signal will be used by the external audio codec device to time its internal circuitry.