3.2.8 Direct Memory Access Controller (DMA)

The Direct Memory Access (DMA) controller is designed to handle high data throughput peripherals on the SFR bus by enabling direct access to data memory to reduce the need for intensive CPU management. The DMA controller is structured with multiple channels, each of which can be connected to a selectable peripheral module. When a peripheral module triggers its interrupt, the corresponding DMA channel responds by accessing the SRAM according to its programming without requiring CPU intervention. This direct access not only frees up the CPU to handle other tasks, but also optimizes overall system efficiency.

Each DMA channel can interrupt the CPU once the DMA session is complete, or if other interrupt conditions are met. This mechanism ensures that the CPU is only engaged when necessary, enhancing system performance and making efficient use of resources. Additionally, this setup helps decrease dynamic power dissipation, especially in applications with lower data throughput demands. By offloading the data transfer tasks from the CPU, the DMA controller significantly contributes to improved system functionality and energy efficiency in a variety of applications.

The DMA Controller has these features:

• Six Independent Channels

• Concurrent Operation with the CPU (No DMA Caused Wait States)

• DMA Bus Arbitration Using Fixed Priority and Round Robin Scheme

• Four Address Modes

• Four Transfer Modes

• 8-Bit, 16-Bit or 32-Bit Word Support for Data Transfer

• 24-Bit Source and Destination Address Register for Each Channel, Dynamically Updated and Independently Reloadable

• 32-Bit Transaction Count Register, Dynamically Updated and Independently Reloadable

• Upper and Lower Address Limit Registers

• Counter Half/Full Level Interrupt

• Software Triggered Transfer

• DMA Request for Each Channel can be Selected From Any Supported Interrupt Source

• Pattern Match

• Bus Read/Write Error Fault Indication