4.5 Instruction Descriptions (C to DTB)

(8’b0, PC[23:2]) → TOS[31:2]; 2’b00 → TOS[1:0],

(W15) + 4 → W15,

lit24 → PC[23:0];

NOP → Instruction Register

The long word aligned return address (PC+4) is pushed onto the system stack. The 24-bit value ‘lit24’ is then loaded into the PC (the opcode does not store the LSb which is always 1’b0).

The ‘n’ bits form the target address.

(8’b0, PC[23:2]) → TOS[31:2]; 2’b00 → TOS[1:0],

(W15)+4 → W15,

Wns[23:0] → PC[23:0];

NOP → Instruction Register.

The long word aligned return address (PC+4) is pushed onto the system stack. The 24-bit value (Wns[23:0]) is then loaded into the PC[23:0]. Wns must therefore contain a PS byte address.

The value of Wns[0] is ignored, and PC[0] is always set to 1’b0.

The ‘s’ bits specify the source register.

The ‘A’ bit selects the accumulator to clear.

0x0000 → file register for word operation

0x00 → file register for byte operation

The ‘L’ and ‘B’ bits select operation data width.

The ‘f’ bits select the address of the file register.

The ‘S’ bit selects instruction size.

The ‘L’ and ‘B’ bits select operation data width.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘d’ bits select the Working register.

The ‘S’ bit selects instruction size.

The ‘L’ and ‘B’ bits select operation data width.

The ‘w’ bits select the Wb source register.

The ‘s’ bits select the Ws source register.

The ‘p’ bits select the source addressing mode.

The Z bit is “sticky” (can only be cleared).

The ‘S’ bit selects instruction size.

The ‘L’ and ‘B’ bits select operation data width.

The ‘w’ bits select the Wb source register.

The ‘s’ bits select the Ws source register.

The ‘p’ bits select the source addressing mode.

or

(Ws) - lit4 - (C)¹

The ‘L’ and ‘B’ bits select operation data width.

The ‘p’ bits select the source addressing mode.

The ‘s’ bits select the source register.

The ‘k’ bits provide the literal operand.

lit13[12:0] = Opcode[12:4], Opcode[23:20]

lit4[3:0] = Opcode[23:20]

The Z bit is sticky (can only be cleared).

The ‘L’ and ‘B’ bits select operation data width.

The ‘p’ bits select the source addressing mode.

The ‘s’ bits select the source register.

The ‘k’ bits provide the literal operand.

lit13[12:0] = Opcode[12:4], Opcode[23:20]

lit4[3:0] = Opcode[23:20]

The Z bit is “sticky” (can only be cleared).

The ‘L’ and ‘B’ bits select operation data width.

The ‘w’ bits select the source register.

The ‘k’ bits provide the literal operand.

The ‘L’ and ‘B’ bits select operation data width.

The ‘f’ bits select the address of the file register.

The ‘s’ bits select the Working register.

Word: (f) - 0x0000

Byte: (f) - 0x00

The ‘L’ and ‘B’ bits select operation data width.

The ‘f’ bits select the address of the file register.

Accessible file address space is 1 MB.

The Z bit is “sticky” (can only be cleared).

The ‘L’ and ‘B’ bits select operation data width.

The ‘f’ bits select the address of the file register.

The ‘s’ bits select the Working register.

The ‘L’ and ‘B’ bits select operation data width.

The ‘w’ bits select the source register.

The ‘k’ bits provide the literal operand.

lit3 → SR.CTX[2:0]

A context switch will update the Current Context Identifier (SR.CTX[2:0]) to reflect the new active CPU register context.

The ‘k’ bits select the target register context.


Wns[2:0] → SR.CTX[2:0]

A context switch will update the Current Context (SR.CTX[2:0]) to reflect the new active CPU register context.

The ‘s’ bits select the source register.

The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘d’ bits select the Working register.

The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘d’ bits select the Working register.

Setting lit3 = 0 will enable all interrupt levels up to and including those at SR.IPL[2:0].

If Wd declared, zero extended prior IPLT[2:0] → Wd[31:0]

The current DISICTL 3-bit IPLT is memory mapped (DISIIPL.IPLT[2:0]) and can be read by the user at any time. A write to DISIIPL will have no effect.

In addition, the IPLT established prior to DISICTL execution may be optionally written to destination Wd if a destination is declared (W = 1). The prior IPLT[2:0] is zero extended to 32-bits prior to being written. If a destination operand is not declared, nothing will be written (W = 0). This facilitates nesting of DISICTL and/or DISICTLW instructions.


The ‘W’ bit determines if a destination write is required.

The ‘k’ bits are an unsigned literal that specifies the DISICTL IPL threshold.

The ‘d’ bits select the destination register.

The ‘q’ bits select the destination addressing mode.

Wns[2:0] = 0 will enable all interrupt levels

If Wd declared, zero extended prior IPLT[2:0] → Wd[31:0]

The current DISICTLW 3-bit IPLT is memory mapped (DISIIPL.IPLT[2:0]) and can be read by the user at any time. A write to DISIIPL will have no effect.

In addition, the IPLT established prior to DISICTL execution may be optionally written to destination Wd if a destination is declared (W = 1). The prior IPLT[2:0] is zero extended to 32-bits prior to being written. If a destination operand is not declared, nothing will be written (W = 0). This facilitates nesting of DISICTL(W) instructions.

This instruction can be used (optionally in conjunction with DISICTLR) to control the impact of system interrupts.

The ‘W’ bit determines if a destination write is required.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘q’ bits select the destination addressing mode.

Wm << 16; 16’b0 → Wm[15:0];

Wm / Wn → 16’b0, Wm[15:0];
Remainder → 16’b0, W(m+1)[15:0]

DIVF.l (32/16); Wm[31:0] = Dividend, Wn[15:0] = Divisor:

Wm / Wn → 16’b0, Wm[15:0];
Remainder → 16’b0, W(m+1)[15:0]

The ‘s’ bits select the source (divisor) register.


Wm / Wn → Wm[31:0]; Remainder → W(m+1)[31:0]


This instruction must be executed ten times to generate the correct quotient and remainder. This may only be achieved by executing a REPEAT with an iteration count of nine (i.e. 9+1 iterations in all) and the DIVFL instruction as its target. The REPEAT loop may be interrupted at any iteration boundary.

C is modified as per the divide algorithm.
Z is set if the remainder is clear. Z is cleared otherwise.
N is set if the remainder is negative. N is cleared otherwise.
OV is set if the divide will result in an overflow. The quotient and remainder will be deterministic but meaningless.

The ‘w’ bits select the source (dividend) register.
The ‘s’ bits select the source (divisor) register.

{16{Wm[15]}}, Wm[15:0] → Wm[31:0];

Wm / Wn → 16’b0, Wm[15:0];
Remainder → 16’b0, W(m+1)[15:0]

DIVS.l (32/16); Wm[31:0] = Dividend, Wn[15:0] = Divisor:

Wm / Wn → 16’b0, Wm[15:0];
Remainder → 16’b0, W(m+1)[15:0]

This instruction must be executed six times to generate the correct quotient and remainder. This may only be achieved by executing a REPEAT with an iteration count of five (i.e. 5+1 iterations in all) and the DIVS instruction as its target. The REPEAT loop may be interrupted at any iteration boundary.



C is modified as per the divide algorithm.


Z is set if the remainder is clear.

Z is cleared otherwise.
N is set if the remainder is negative.

N is cleared otherwise.
OV is set if the divide will result in an overflow.

OV is cleared otherwise. The quotient and remainder will be deterministic but meaningless.

The ‘L’ bit selects 32-bit or 16-bit dividend size.

The ‘w’ bits select the source (dividend) register.

The ‘s’ bits select the source (divisor) register.

Wm / Wn → Wm; Remainder → W(m+1)

This instruction must be executed ten times to generate the correct quotient and remainder. This may only be achieved by executing a REPEAT with an iteration count of nine (i.e. 9+1 iterations in all) and the DIVSL instruction as its target. The REPEAT loop may be interrupted at any iteration boundary.



C is modified as per the divide algorithm.


Z is set if the remainder is clear. Z is cleared otherwise.


N is set if the remainder is negative. N is cleared otherwise.


OV is set if the divide will result in an overflow. OV is cleared otherwise. The quotient and remainder will be deterministic but meaningless.



The ‘w’ bits select the source (dividend) register.

The ‘s’ bits select the source (divisor) register.

16’b0 → Wm[31:16];

Wm / Wn → 16’b0, Wm[15:0]; Remainder → 16’b0, W(m+1)[15:0]

DIVU.l (32/16); Wm[31:0] = Dividend, Wn[15:0] = Divisor:

Wm / Wn → 16’b0, Wm[15:0]; Remainder → 16’b0, W(m+1)[15:0]

This instruction must be executed six times to generate the correct quotient and remainder. This may only be achieved by executing a REPEAT with an iteration count of five (i.e. 5+1 iterations in all) and the DIVU instruction as its target. The REPEAT loop may be interrupted at any iteration boundary.



C is modified as per the divide algorithm.


Z is set if the remainder is clear. Z is cleared otherwise.


N is always cleared.
 OV (DIVU.w) is always cleared because an overflow is not possible.

OV (DIVU.l) is set if the divide will result in an overflow.

OV is cleared otherwise. 

The ‘L’ bit selects 32-bit or 16-bit dividend size.

The ‘w’ bits select the source (dividend) register.

The ‘s’ bits select the source (divisor) register.

Wm / Wn → Wm; Remainder → W(m+1)

This instruction must be executed ten times to generate the correct quotient and remainder. This may only be achieved by executing a REPEAT with an iteration count of nine (i.e. 9+1 iterations in all) and the DIVUL instruction as its target. The REPEAT loop may be interrupted at any iteration boundary.



C is modified as per the divide algorithm.


Z is set if the remainder is clear.

Z is cleared otherwise.


N is always cleared.


OV is always cleared because an overflow is not possible.



The ‘w’ bits select the source (dividend) register.

The ‘s’ bits select the source (divisor) register.

Label is resolved by the linker to a signed word offset (slit16)

If (Wn != 0 [see text]) then {

If slit16 = 1 then skip next (16-bit) instruction

Else if (slit16 = 2 && next_op[31] = 1) then skip next (32-bit) instruction

Else (PC+4) + 2*slit16 → PC

}

Else No branch

When utilized as a code block loop counter where DTB is located at the end of the loop, DTB will iterate the loop (i.e., branch) Wn times and will exit the loop with Wn = 0x0000_0000 (see note 2).

If the branch condition is met, then the instruction will either skip the next 16-bit or 32-bit instruction, or it will branch to any size of instruction with a forward or backward range of 64KB.

If the 2’s complement byte offset value ‘2*slit16’ (the PC offset) equals two, the conditional branch will execute as a conditional skip of one 16-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If the 2’s complement byte offset value ‘2*slit16’ (the PC offset) equals four and the instruction after the branch is a 32-bit opcode (see note), the conditional branch will execute as a conditional skip of that 32-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If requirements for a conditional skip are not met, the 2’s complement byte offset value ‘2*slit16’ is added to the PC to create a new PS word address. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+4) + 2*slit16.

Branch prediction is based on the direction of the branch. If the branch is backwards (negative), it will be predicted as taken. If the branch is forwards (positive), it will be predicted as not taken. The two instructions that follow the branch will then be speculatively executed in the predicted path until such time that the actual branch decision can be assessed. A correctly predicted branch will continue instruction execution in the same path unabated. An incorrectly predicted branch will abort the speculatively executed instructions and start execution from the correct path.

The ‘n’ bits are a signed literal that specifies the number of PS words offset from (PC+4).