4.2 Instruction Encoding Field Descriptors Introduction

All instruction encoding field descriptors used in Instruction Descriptions are shown in Table 4-2 through Table 4-10.

Table 4-1. Instruction Encoding Field Descriptors
FieldDescription
AAccumulator Selection bit: 0 = ACCA; 1 = ACCB
aaaAccumulator Write Back mode (see Table 4-9)
BByte Mode Selection bit: 0 = word operation; 1 = byte operation
bbb3-bit bit position select: 000 = LSB; 111 = MSB
bbbb5-bit bit position select: 00000 = LSB; 11111 = MSB
ccccBit field instructions LSb value
DDestination Address bit: 0 = result stored in W0; 1 = result stored in file register
ddddWd destination register select: 0000 = W0; 1111 = W15
dddddCoprocessor destination register select (Fd for FPU where 00000 = F0; 11111 = F31)
EMULxx Result size: 0 = 32-bit in Wnd; 1 = 64-bit in (Wnd+1, Wnd)
FSelects between W15 (F = 0) and W14 (F = 1) registers
(ffff) ffff ffff ffff ffff16-bit or 20-bit register file address (addressable space varies depending upon instruction class)
GBit test destination: 0 = Z flag bit; 1 = C flag bit
IMULAxx Multiply mode: 0 = Fractional; 1 = Integer
IIIiiX data fetch operation
JJJjjY data fetch operation
k1-bit literal field, constant data
kkk3-bit literal field, constant data
k kkkk5-bit literal field, constant data
kk kkkk6-bit literal field, constant data
kkkk kkkk8-bit literal field, constant data
kkkk kkkk kkkk kkkk16-bit literal field, constant data

kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk

32-bit literal field, constant data
LLong (32-bit) Mode Selection bit: 0 = word or byte operation; 1 = long operation
mmmmmBit field instructions MSb value
nnnn nnnn nnnn nnnn nnnn n21-bit signed instruction word offset field for relative branch/call instructions
nnnn nnnn nnnn nn00 nnnn nnnn24-bit program address for goto/call instructions
pppAddressing mode for Ws source register (see Table 4-2)
qqqAddressing mode for Wd destination register (see Table 4-3)
RSelects between FPU coprocessor special registers or F-regs
rrrCondition select for conditional move (MOVIF) instruction
SOpcode size select (16-bit: S = 0; 32-bit: S = 1)
ssssWs source or Wn source/destination register select: 0000 = W0; 1111 = W15
sssssCoprocessor source register select (Fs for FPU where 00000 = F0; 11111 = F31)
TSelects between Ws (T = 0) and SR (T = 1) target registers
UUnused (don’t care) Instruction bit. Assembler to assign ‘0’
VFLIMW: Selects result format for Wnd (refer to instruction description) MULxx: Selects between unsigned Ws (V = 0) and signed Ws (V = 1).
WDestination write control: 0 = Wd write not required; 1 = Wd write required
wwwwSource Wb base register select: 0000 = W0; 1111 = W15
zzCoprocessor select
Table 4-2. Addressing Modes for Ws Source Register
pppAddressing ModeSource Operand
000Register DirectWns
001Indirect[Ws]
010Indirect with Post-Decrement[Ws--]
011Indirect with Post-Increment[Ws++]
100Indirect with Pre-Decrement[--Ws]
101Indirect with Pre-Increment[++Ws]
110Status Register DirectSR (Source)
111Indirect with Register Offset[Ws+Wb]
Table 4-3. Addressing Modes for Wd Destination Register
qqqAddressing ModeDestination Operand
000Register DirectWnd
001Indirect[Wd]
010Indirect with Post-Decrement[Wd--]
011Indirect with Post-Increment[Wd++]
100Indirect with Pre-Decrement[--Wd]
101Indirect with Pre-Increment[++Wd]
110Status Register (SR) DirectSR (Destination)
111Indirect with Register Offset [Wd+Wb]
Table 4-4. Destination Addressing Modes for MCU Multiplications
ddddDestination
0000W1:W0
0001W0
0010W3:W2
0011W2
0100W5:W4
0101W4
0110W7:W6
0111W6
1000W9:W8
1001W8
1010W11:W10
1011W10
1100W13:W12
1101W12
1110ACCA[39:0]
1111ACCB[39:0]
Table 4-5. Offset Addressing Modes for Ws Source Register (with Register Offset)
gggAddressing ModeSource Operand
000Register DirectWs
001Indirect[Ws]
010Indirect with Post-Decrement[Ws--]
011Indirect with Post-Increment[Ws++]
100Indirect with Pre-Decrement[--Ws]
101Indirect with Pre-Increment[++Ws]
11xIndirect with Register Offset[Ws+Wb]
Table 4-6. Offset Addressing Modes for Wd Destination Register
(with Register Offset)
hhhAddressing ModeSource Operand
000Register DirectWd
001Indirect[Wd]
010Indirect with Post-Decrement[Wd--]
011Indirect with Post-Increment[Wd++]
100Indirect with Pre-Decrement[--Wd]
101Indirect with Pre-Increment[++Wd]
11xIndirect with Register Offset[Wd+Wb]
Table 4-7. MAC or MPY Source Operands – Same Working Register
mmMultiplicands
00W4 * W4
01W5 * W5
10W6 * W6
11W7 * W7
Table 4-8. MAC or MPY Source Operands – Different Working Register
mmmMultiplicands
000W4 * W5
001W4 * W6
010W4 * W7
011Invalid
100W5 * W6
101W5 * W7
110W6 * W7
111Invalid
Table 4-9. MAC Accumulator Write-Back Selection
aaaWrite-Back Selection
000W0 = Other Accumulator
001W1 = Other Accumulator
010W2 = Other Accumulator
011W3 = Other Accumulator
100W13 = Other Accumulator (Direct Addressing)
101[W13++] = Other Accumulator (Indirect Addressing with Post-Increment)
110[W15++] = Other Accumulator
111No Accumulator Write Back
Table 4-10. Accumulator Selection
ATarget Accumulator
0Accumulator A
1Accumulator B