4.9 Floating-Point Instruction Description


ABS		Absolute value of Fs
Syntax:	{label:}	ABS.s	Fs,	Fd
		ABS.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	ABS Fs → Fd
Status Affected:	SUBO
Exceptions Possible:	SUBO
Encoding:	`1000`	`100P`	`zzdd`	`ddds`	`ssss`	`UUUU`	`UUUU`	`0010`
Description:	Clear the sign of the contents of the source register Fs, and place the result in the destination register Fd. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘`s`’ bits select the source register. The ‘`d`’ bits select the destination register.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1

Note: This instruction only affects the sign bit and will not quit an sNaN input operand.


ABS.s	F0, F3	;Find absolute value of a number in F0 and store result in F3

Before execution			After execution
F0	0x40800001	-1.0000001	F0	0x40800001
F3	0x00000000		F3	0x40800001

FSR[7:0]	8'b00000000		FSR[7:0]	8'b00000000


ABS.d F0, F2
Before execution		After execution
F1:F0	0x8000000000000001	F1:F0	0x8000000000000001
F3:F2	0x0000000000000000	F3:F2	0x0000000000000001

FSR[7:0]	8'b00000000	FSR[7:0]	8'b01000000(SUBO)	(SUBO)


ADD		Add Fb and Fs
Syntax:	{label:}	ADD.s Fb,		Fs,	Fd
		ADD.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	Fb + Fs → Fd
Status Affected:	SUBO, INX, UDF, OVF, INVAL (see Note 1)
Exceptions Possible:	SUBO, INX, UDF, OVF, INVAL
Encoding:	`1000`	`000P`	`zzdd`	`ddds`	`ssss`	`wwww`	`wUUU`	`0010`
Description:	Add the contents of the source register Fb and the contents of the register Fs, then place the result in the destination register Fd. (∞ + (-∞)) will result in distinguished qNaN and signal an INVAL exception. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	2
DP Execute Cycles:	2
Repetition Rate:	1


AND		AND Floating-Point Control/Status Register and Literal
Syntax:	{label:}	AND	lit16,	FSR
				FCR
				FEAR




Operand	lit16 ∈ [0 ... 65535]
Operation:	(FP special register[15:0]).AND.lit16 → FP special register[15:0]
Status Affected:	None (other than as a result of the instruction AND operation)
Exceptions Possible:	None
Encoding:	`1001`	`000U`	`zzss`	`kkkk`	`kkkk`	`kkkk`	`kkkk`	`0010`
Description:	Compute the AND of the lsw contents of the selected floating-point coprocessor special register and the literal operand, and write the result back into the lsw of the selected register. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the floating-point coprocessor source register. The ‘k’ bits specify the 16-bit literal operand. Note: Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro. The effect of this instruction is solely to clear bits within the target register. No FPU interrupts can result from its execution. FEAR destination includes the EACE control/status bit.
I-Words:	1
Execute Cycles:	1
Repetition Rate:	1


AND	#FFF8, FCR	;FCR \| 0x7 -> To clear INVAL, DIV0 and OVM masks

Before execution		After execution
FCR	0x00000300	FCR	0x00000307


COS		Evaluate the Cosine of Fs
Syntax:	{label:}	COS.s	Fs,	Fd



Operands (.s):	Fs ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operation:	cos(Fs) → Fd
Status Affected:	SUBO, INX, UDF, INVAL (see Note 1)
Exceptions Possible:	SUBO, INX, UDF, INVAL
Encoding:	`1000`	`110P`	`zzdd`	`ddds`	`ssss`	`UUUU`	`UUUU`	`0110`
Description:	Calculate the cosine of the contents of the source register Fs (where Fs = [2πk + θ rads]), and place the result in the destination register Fd. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. This operation is only supported using single precision floating-point. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	4
Repetition Rate:	1


COS.s	F0, F3

Before execution		After execution
F0	0x4016DB6E	F0	0x4016DB6E
F3	0x00000000	F3	0xBF3530E2

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


COS.s	F0, F3

Before execution		After execution
F0	0xFF800000	F0	0xFF800000
F3	0x00000000	F3	0x7FC00001	(distinguished qNaN)

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000001	(INVAL)


CPQ		Compare Fb with Fs, Quiet Signaling
Syntax:	{label:}	CPQ.s	Fb,	Fs
		CPQ.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]
Operation:	Fb - Fs (with IEEE signaling predicates)
Status Affected:	LT, GT, EQ, UN, SUBO, INVAL (see Note 1)
Exceptions Possible:	SUBO, INVAL
Encoding:	`1000`	`101P`	`zzUU`	`UUUs`	`ssss`	`wwww`	`wUUU`	`1010`
Description:	Compare of the contents of the source registers Fb and Fs (Fb - Fs) then set flags, but do not store the result. An Invalid signaling exception will only be generated if either source operand is a sNaN. A qNaN source operand will not result in a signaling exception. If any source operand is a sNaN or qNaN, then set FSR.UN = 1. The LT, GT and EQ status bits are set depending on the result. The ‘P’ bit selects single (32-bit) or double precision (64-bit) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro. This instruction considers -0 and +0 as equivalent.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1


CPQ.s	F0, F3
Before execution		After execution
F0	0xFF7FFFFB	F0	0xFF7FFFFB
F3	0x80800001	F3	0x80800001

FSR[23:16]	8'b00000000	FSR[23:16]	8'b00000100	(LT)


CPQ.d	F0, F2

Before execution		After execution
F1:F0	0xFFF800000000000E	F1:F0	0xFFF800000000000E
F3:F2	0xFFF8000000000008	F3:F2	0xFFF8000000000008

FSR[23:16]	8'b00000000	FSR[23:16]	8'b00000001	(UN)
FSR[7:0]	8'b00000000	FSR[23:16]	8'b00000000


CPS		Compare Fb with Fs, Signaling
Syntax:	{label:}	CPS.s	Fb,	Fs
		CPS.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]
Operation:	Fb - Fs (with IEEE signaling predicates)
Status Affected:	LT, GT, EQ, UN, SUBO, INVAL (see Note 1)
Exceptions Possible:	SUBO, INVAL
Encoding:	`1000`	`101P`	`zzUU`	`UUUs`	`ssss`	`wwww`	`wUUU`	`1110`
Description:	Compare of the contents of the source registers Fb and Fs (Fb - Fs) then set flags, but do not store the result. If either source operand is a sNaN or a qNaN, an Invalid signaling exception will be generated. If any source operand is a sNaN or qNaN, then set FSR.UN = 1. The LT, GT and EQ status bits are set depending on the result. The ‘P’ bit selects single (32-bit) or double precision (64-bit) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro. This instruction consider -0 and +0 as equivalent.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1


CPS.s	F0, F3

Before execution		After execution
F0	0xFF7FFFFB	F0	0xFF7FFFFB
F3	0x80800001	F3	0x80800001

FSR[23:16]	8'b00000000	FSR[23:16]	8'b00000100	(LT)


CPS.d	F0, F2

Before execution		After execution
F1:F0	0xFFF800000000000E	F1:F0	0xFFF800000000000E
F3:F2	0xFFF8000000000008	F3:F2	0xFFF8000000000008

FSR[23:16]	8'b00000000	FSR[23:16]	8'b00000001	(UN)
FSR[7:0]	8'b00000000	FSR[23:16]	8'b00000001	(INVAL)


DI2F		Convert Double Word (64-bit) Integer to Floating Point
Syntax:	{label:}	DI2F.s{rnd}		Fs,	Fd
		DI2F.d{rnd}


Operands (.s):	Fs ∈ [F0, F2 ... F30]; Fd ∈ [F0 ... F31]; rnd ∈ [e, z, p, n]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]; rnd ∈ [e, z, p, n]
Operation:	Fs (integer) → Fd (float)
Status Affected:	INX¹
Exceptions Possible:	INX
Encoding:	`1000`	`111P`	`zzdd`	`ddds`	`ssss`	`UUUU`	`Ueee`	`1110`
Description:	Convert the 64-bit integer contents of the source register Fs to floating point, round, then place the result in the destination register Fd. If rounding mode {rnd} is not specified, it will default to that defined by FCR.RND[1:0]. If the integer cannot be represented exactly as a floating point value, the Inexact signaling exception will be generated. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘e’ bits define the rounding mode applied. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	2
DP Execute Cycles:	2
Repetition Rate:	1


DI2F.sp F0, F2	;Convert 64-bit double long-word integer to a SP floating-point value (with rounding = pos)

Before execution		After execution
F1:F0	0x7FFFFFFFFFFFFFFB	F1:F0	0x7FFFFFFFFFFFFFFB
F2	0x00000000	F2	0x5EFFFFFF

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00010000	(INX)


DI2F.dz F0, F2			;Convert 64-bit double long-word integer to a DP floating-point value (with rounding = zero)
Before execution		After execution
F1:F0	0xFFFFFFFFFFFFFFFF	F1:F0	0xFFFFFFFFFFFFFFFF
F3:F2	0x0000000000000000	F3:F2	0xBFF0000000000000


DIV		Signed Floating-Point Divide
Syntax:	{label:}	DIV.s	Fb	Fs,	Fd
		DIV.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	Fb ÷ Fs → Fd
Status Affected:	SUBO, INX, UDF, OVF, DIV0, INVAL (see Note 1)
Exceptions Possible:	SUBO, INX, UDF, OVF, DIV0, INVAL
Encoding:	`1000`	`010P`	`zzdd`	`ddds`	`ssss`	`wwww`	`wUUU`	`1010`
Description:	Divide the contents of the source register Fb with the contents of the source register Fs, then place the result in the destination register Fd. Result of (∞/0) is correctly signed infinity. Whereas, ((0/0) or (∞/∞)) will result in distinguished qNaN and signal an FPU INVAL exception. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. An attempt to divide by zero may or may not signal DIV0 depending upon operands. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	11
DP Execute Cycles:	32


DIV.s F0, F1, F3

Before execution		After execution
F0	0x7F00000A	F0	0x7F00000A
F1	0xFF0000AA	F1	0xFF0000AA
F3	0x00000000	F3	0xBF7FFEC0

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


DIV.d F0, F4, F8

Before execution		After execution
F1:F0	0xFFEA36E2EB1C432D	F1:F0	0xFFEA36E2EB1C432D
F5:F4	0x0000000000A00000	F5:F4	0x0000000000A00000
F9:F8	0x0000000000000000	F9:F8	0xFFEFFFFFFFFFFFFF

FSR[7:0]	8'b00000000	FSR[7:0]	8'b01010100	(INX, OVF, SUBO)


FLIM		Force Signed Data Limit
Syntax:	{label:}	FLIM.s	Fb,	Fs,	Fd
		FLIM.d




Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	IF (Fd) > (Fs) THEN (Fs) → (Fd); IF (Fd) < (Fb) THEN (Fb) → (Fd);
Status Affected:	SUBO, INVAL (see Note 1)
Exceptions Possible:	SUBO, INVAL
Encoding:	`1001`	`001P`	`zzdd`	`ddds`	`ssss`	`wwww`	`wUUU`	`0010`
Description:	Simultaneously compare a signed floating-point value in Fd to a maximum signed floating-point value held in Fs and a minimum signed floating-point value held in Fb. If Fd is greater than Fs, set Fd to the limit value held in Fs. If Fd is less than Fb, set Fd to the limit value held in Fb. If Fd is less than or equal to the maximum limit value in Fs, and greater than or equal to the minimum limit value in Fb, Fd is not modified (i.e., data is within range and limits are not applied). See note 2. If any of the operands (limit values or value to be tested) are an sNaN or a qNaN, the instruction will return a qNaN as the result. In addition, if any of the operands are an sNaN, the INVAL status will be set. Should the (maximum) limit value Fs be inadvertently set to less than (minimum) limit value Fb, the instruction will return the distinguished qNaN as the result and set the INVAL status. This is a signed comparison operation. The limits may both be of the same sign. The ‘P’ bit selects single (32-bit) or double precision (64-bit) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1


FLIM.s F3, F0, F1

Before execution		After execution
F0	0xFF669595	F0	0xFF000000
F1	0xFF000000	F1	0xFF000000
F3	0x44480000	F3	0x44480000


FLIM.d F6, F4, F0

Before execution		After execution
F1:F0	0xC024000000000000	F1:F0	0xC014000000000000
F5:F4	0x4024000000000000	F5:F4	0x4024000000000000
F9:F8	0xC014000000000000	F9:F8	0xC014000000000000


F2DI		Convert Floating-Point Fs to Double Word (64-bit) Integer
Syntax:	{label:}	F2DI.s{rnd}		Fs,	Fd
		F2DI.d{rnd}




Operands (.s):	Fs ∈ [F0 ... F31]; Fd ∈ [F0, F2 ... F30]; rnd ∈ [e, z, p, n]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]; rnd ∈ [e, z, p, n]
Operation:	Fs (float) → Fd (integer)
Status Affected:	SUBO, HUGI, INX, INVAL (see Note 1)
Exceptions Possible:	SUBO, HUGI, INX, INVAL
Encoding:	`1000`	`111P`	`zzdd`	`ddds`	`ssss`	`UUUU`	`Ueee`	`0110`
Description:	Convert the floating-point contents of the source register Fs to a rounded 64-bit integer, then place the result in the destination register Fd. If rounding mode {rnd} is not specified, it will default to that defined by FCR.RND[1:0]. If the source register contains ±NaN or ±∞, the INVAL exception will be signaled and the result will be the integer indefinite value of 0x8000_0000_0000_0000 (maximum negative integer). If the source register contains a finite floating point number, but the result rounds to a number greater than 2⁶³-1 or less than -2⁶³, the HUGI and INVAL exceptions will be signaled and the default result will be the integer indefinite value of 0x7FFF_FFFF_FFFF_FFFF or 0x8000_0000_0000_0000, respectively. If the source register contains a subnormal value, the result will always be zero and the INX exception will be signaled.  The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘e’ bits define the rounding mode applied. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	1 (subject to change)
DP Execute Cycles:	2 (subject to change)
Repetition Rate:	1


F2DI.sp F0, F2	;Convert SP float value to a 64-bit double long-word integer(with rounding = pos)

Before execution		After execution
F0	0xD7FFFFFE	F0	0xD7FFFFFE
F3:F2	0x0000000000000000	F3:F2	0xFFFE000004000000

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00010000	(INX)


F2DI.dz F0, F2	;Convert DP float value to a 64-bit double long-word integer(with rounding = zero)

Before execution		After execution
F1:F0	0xC2E4F8B5877B8000	F1:F0	0xC2E4F8B5877B8000
F3:F2	0x0000000000000000	F3:F2	0xFFFF583A53C42400


F2LI		Convert Floating-Point Fs to Long Word (32-bit) Integer
Syntax:	{label:}	F2LI.s{rnd}		Fs,	Fd
		F2LI.d{rnd}


Operands (.s):	Fs ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]; rnd ∈ [e, z, p, n]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fd ∈ [F0 ... F31]; rnd ∈ [e, z, p, n]
Operation:	Fs (float) → Fd (integer)
Status Affected:	SUBO, HUGI, INX, INVAL (see Note 1)
Exceptions Possible:	SUBO, HUGI, INX, INVAL
Encoding:	`1000`	`111P`	`zzdd`	`ddds`	`ssss`	`UUUU`	`Ueee`	`0010`
Description:	Convert the floating-point contents of the source register Fs to a rounded 32-bit integer, then place the result in the destination register Fd. If rounding mode {rnd} is not specified, it will default to that defined by FCR.RND[1:0]. If the source register contains ±NaN or ±∞, the INVAL exception will be signaled and the result will be the integer indefinite value of 0x8000_0000 (maximum negative integer). If the source register contains a finite floating-point number but the result rounds to a number greater than 2³¹-1 or less than -2³¹, the HUGI and INVAL exceptions will be signaled and the default result will be the integer indefinite value of 0x7FFF_FFFF or 0x8000_0000, respectively. If the source register contains a subnormal value, the result will always be zero and the INX exception will be signaled. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘e’ bits define the rounding mode applied. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	2
Repetition Rate:	1


F2LI.sp F0, F1	;Convert SP float value to a long-word integer(with rounding = pos)

Before execution		After execution
F0	0xCA0EF725	F0	0xCA0EF725
F1	0x00000000	F1	0xFFDC4237

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00010000	(INX)


F2LI.dz F0, F2	;Convert DP float value to a long-word integer(with rounding = zero)

Before execution		After execution
F1:F0	0xC09F400000000000	F1:F0	0xC09F400000000000
F2	0x00000000	F2	0xFFFFF830

FBRA CC FPU Coprocessor Branch

Syntax: {label:} FBRA CC, Expr

Operands: Expr is resolved by the linker to a signed word offset (slit20)

Operation:

Condition (cc) = See Table x.y

If (cc) then {

If slit20 = 1 then skip next (16-bit) instruction

Else if (slit20 = 2 && next_op[31] = 1) then skip next (32-bit) instruction

Else (PC+4) + 2*slit20 → PC

}

Else no branch

Status Affected: None

Encoding: 1011 bbbb nnnn nnnn nnnn nnnn nnnn zz10

See Table 4-13 for the value of “bbbb”

Description:

If the branch condition is met, then the instruction will either skip the next 16-bit or 32-bit instruction, or it will branch to any size of instruction with a forward or backward range of 1MB.

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals two, the conditional branch will execute as a conditional skip of one 16-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If the 2’s complement byte offset value ‘2*slit20’ (the PC offset) equals four and the instruction after the branch is a 32-bit opcode (see note), the conditional branch will execute as a conditional skip of that 32-bit instruction. This instruction will be speculatively executed as not skipped until such time that the branch decision can be determined.

If requirements for a conditional skip are not met, the 2’s complement byte offset value ‘2*slit20’ is added to the PC to create a new PS word address. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+4) + 2*slit20.

Branch prediction is based on the direction of the branch. If the branch is backwards (negative), it will be predicted as taken. If the branch is forwards (positive), it will be predicted as not taken.

The two instructions that follow the branch will then be speculatively executed in the predicted path until such time that the actual branch decision can be assessed. A correctly predicted branch will continue instruction execution in the same path unabated. An incorrectly predicted branch will abort the speculatively executed instructions and start execution from the correct path.

The ‘n’ bits are a signed literal that specifies the number of PS words offset from (PC+4).

The ‘z’ bits select the target coprocessor.

FPU co-processor supports number of branch conditions (cc) as mentioned in folloowing table.

Table 4-13. FBRA Conditions
cc	Conditions	Encoding (bbbb)
EQ	FSR.EQ	0000
UNE	(FSR.GT \|\| FSR.LT \|\| FSR.UN)	0001
NE	(FSR.GT \|\| FSR.LT)	0010
UEQ	(FSR.EQ \|\| FSR.UN)	0011
GT	FSR.GT	0100
ULE	(FSR.LT \|\| FSR.EQ \|\| FSR.UN)	0101
GE	(FSR.GT \|\| FSR.EQ)	0110
ULT	(FSR.LT \|\| FSR.UN)	0111
LT	FSR.LT	1000
UGE	(FSR.GT \|\| FSR.EQ \|\| FSR.UN)	1001
LE	(FSR.LT \|\| FSR.EQ)	1010
UGT	(FSR.GT \|\| FSR.UN)	1011
OR	(FSR.GT \|\| FSR.LT \|\| FSR.EQ)	1100
UN	FSR.UN	1101

Note:

Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
Should the byte offset equal four and instruction after the branch is a 16-bit opcode, a branch will occur (over the next two 16-bit ops) if the condition is met.
Branch conditions are evaluated within the coprocessor.

I-Words: 1

Cycles: 1 (2 or 3)


IOR		Inclusive OR Floating-Point Control/Status Register and Literal
Syntax:	{label:}	IOR	lit16,	FSR
				FCR
				FEAR




Operand	lit16 ∈ [0 ... 65535]
Operation:	(FP special register[15:0]).IOR.lit16 → FP special register[15:0]
Status Affected:	None (other than as a result of the instruction OR operation)
Exceptions Possible:	None
Encoding:	`1001`	`000U`	`zzss`	`kkkk`	`kkkk`	`kkkk`	`kkkk`	`0110`
Description:	Compute the inclusive OR of the contents of the lsw of the selected floating-point coprocessor register and the literal operand, and write the result back into the lsw of the selected register. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the floating-point coprocessor source register. The ‘k’ bits specify the 16-bit literal operand. Note: Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro. The effect of this instruction is solely to set bits within the target register. No FPU interrupts can result from its execution. FEAR destination includes the EACE control/status bit.
I-Words:	1
Execute Cycles:	1
Repetition Rate:	1


IOR #7, FCR	;FCR \| 0x7 -> To set INVAL, DIV0 and OVM masks

Before execution		After execution
FCR	0x00000300	FCR	0x00000307


LI2F		Convert Long Word (32-bit) Integer to Floating-Point
Syntax:	{label:}	LI2F.s{rnd}		Fs,	Fd
		LI2F.d{rnd}


Operands (.s):	Fs ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]; rnd ∈ [e, z, p, n]
Operands (.d):	Fs ∈ [F0 ... F31]; Fd ∈ [F0, F2 ... F30]; rnd ∈ [e, z, p, n]³
Operation:	Fs (integer) → Fd (float)
Status Affected:	INX^{1, 3}
Exceptions Possible:	INX
Encoding:	`1000`	`111P`	`zzdd`	`ddds`	`ssss`	`UUUU`	`Ueee`	`1010`
Description:	Convert the 32-bit integer contents of the source register Fs to floating-point, round, and then place the result in the destination register Fd. If rounding mode {rnd} is not specified, it will default to that defined by FCR.RND[1:0]. If the integer cannot be represented exactly as a floating-point value, the Inexact signaling exception will be generated (see note 3). The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘e’ bits define the rounding mode applied. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro. Long integer to Double Precision float (LI2F.d) conversion are always exact, so Inexact (INX) status will never be set. Similarly, rounding modes will have no effect on LI2F.d result.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1


LI2F.se F0, F1	;Convert long-word integer to SP float value (with even rounding)

Before execution		After execution
F0	0xFFFFF830	F0	0xFFFFF830
F1	0x00000000	F1	0xC4FA0000


LI2F.d F0, F2	;Convert long-word integer to DP float value

Before execution		After execution
F0	0xAFF0BDBC	F0	0xAFF0BDBC
F3:F2	0x0000000000000000	F3:F2	0xC1D403D091000000


MAC		Floating-Point Signed Multiply and Accumulate
Syntax:	{label:}	MAC.s	Fb,	Fs,	Fd
		MAC.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	(Fd) + ((Fb) * (Fs)) → Fd;
Status Affected:	SUBO, INX, UDF, OVF, INVAL (see Note 1)
Exceptions Possible:	SUBO, INX, UDF, OVF, INVAL
Encoding:	`1000`	`010P`	`zzdd`	`ddds`	`ssss`	`wwww`	`wUUU`	`0010`
Description:	Multiply the signed contents of the source register Fb with the signed contents of the source register Fs, then add the product to Fd. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	3
DP Execute Cycles:	4
Repetition Rate:	1


MAC.s F3, F0, F1

Before execution		After execution
F0	0x80FFFFFF	F0	0x80FFFFFF
F1	0x00000000	F1	0x00000000
F3	0x80FFFFFE	F3	0x00000000

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00011000	(UDF, INX)


MAC.d F6, F4, F0

Before execution		After execution
F1:F0	0x4069000000000000	F1:F0	0x4069000000000000
F5:F4	0x407F400000000000	F5:F4	0x407F400000000000
F9:F8	0x4024000000000000	F9:F8	0x40A3880000000000

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


MAX		Select the Signed Maximum of Fb and Fs {IEEE 754-2019 maximum(x,y)}
Syntax:	{label:}	MAX.s Fb,		Fs,	Fd
		MAX.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	IF (Fs) >= (Fb) THEN (Fs) → (Fd); ELSE (Fb) → (Fd)
Status Affected:	SUBO, INVAL (see Note 1)
Exceptions Possible:	SUBO, INVAL
Encoding:	`1000`	`001P`	`zzdd`	`ddds`	`ssss`	`wwww`	`wUUU`	`0010`
Description:	Find the signed maximum of two floating-point values held in Fb and Fs. This instruction is compliant with the IEEE 754-2019 maximum() operation. Compare the contents of the source registers Fb and Fs, then place the maximum of the two values in the destination register Fd. This is a signed comparison operation (see note 3). If Fb = Fs (and of the same sign), Fd is loaded with the contents of Fs. When one (or both) of the input operands is a NaN, the instructions will return a qNaN. The ‘P’ bit selects single (32-bit) or double precision (64-bit) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro. Operand value of -0 compares to less than +0.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1


MAX.s F0, F1, F3

Before execution		After execution
F0	0x7F800000	F0	0x7F800000
F1	0xFF800000	F1	0xFF800000
F3	0x00000000	F3	0x7F800000

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


MAX.d F0, F4, F8

Before execution		After execution
F1:F0	0x000000000000000A	F1:F0	0x000000000000000A
F5:F4	0xC00000000000000C	F5:F4	0xC00000000000000C
F9:F8	0x00000000000000	F9:F8	0x000000000000000A

FSR[7:0]	8'b00000000	FSR[7:0]	8'b01000000	(SUBO)


MAXNM		Select the Signed Maximum of Fb and Fs {IEEE 754-2019 maxmumNumber(x,y)}
Syntax:	{label:}	MAXNM.s Fb,		Fs,	Fd
		MAXNM.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	IF (Fs) >= (Fb) THEN (Fs) → (Fd); ELSE (Fb) → (Fd)
Status Affected:	SUBO, INVAL (see Note 1)
Exceptions Possible:	SUBO, INVAL
Encoding:	`1000`	`001P`	`zzdd`	`ddds`	`ssss`	`wwww`	`wUUU`	`0110`
Description:	Find the signed maximum of two floating-point values held in Fb and Fs. This instruction is compliant with the IEEE 754-2019 maximumNumber() operation. Compare the contents of the source registers Fb and Fs, then place the maximum of the two values in the destination register Fd. If Fb = Fs, Fd is loaded with the contents of Fs. This is a signed comparison operation (see note 3). If Fb = Fs (and of the same sign), Fd is loaded with the contents of Fs. When one of the input operands is a NaN and the other input is a floating-point number (that is not a NaN), the instructions will return the floating-point number. If both input operands are a NaN, the instructions will return a qNaN. The ‘P’ bit selects single (32-bit) or double precision (64-bit) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro. Operand value of -0 compares to less than +0.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1


MAXNM.s F0, F1, F3

Before execution		After execution
F0	0x00000000	F0	0x00000000
F1	0x80000000	F1	0x80000000
F3	0x00000000	F3	0x00000000

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


MAXNM.d F0, F4, F8

Before execution		After execution
F1:F0	0x800000000000000A	F1:F0	0x800000000000000A
F5:F4	0x3FF924920048245C	F5:F4	0x3FF924920048245C
F9:F8	0x00000000000000	F9:F8	0x3FF924920048245C

FSR[7:0]	8'b00000000	FSR[7:0]	8'b01000000	(SUBO)


MIN		Select the Signed Minimum of Fb and Fs  {IEEE 754-2019 minimum(x,y)}
Syntax:	{label:}	MIN.s	Fb,	Fs,	Fd
		MIN.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	IF (Fs) <= (Fb) THEN (Fs) → (Fd); ELSE (Fb) → (Fd)
Status Affected:	SUBO, INVAL (see note 1)
Exceptions Possible:	SUBO, INVAL
Encoding:	`1000`	`001P`	`zzdd`	`ddds`	`ssss`	`wwww`	`wUUU`	`1010`
Description:	Find the signed minimum of two floating-point values held in Fb and Fs. This instruction is compliant with the IEEE 754-2019 minimum() operation. Compare the contents of the source registers Fb and Fs, then place the minimum of the two values in the destination register Fd. This is a signed comparison operation (see note 3). If Fb = Fs (and of the same sign), Fd is loaded with the contents of Fs. When one (or both) of the input operands is a NaN, the instructions will return a qNaN. The ‘P’ bit selects single (32-bit) or double precision (64-bit) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. Note: If not already set, corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro. Operand value of -0 compares to less than +0.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1


MIN.s F0, F1, F3

Before execution		After execution
F0	0x7F800000	F0	0x7F800000
F1	0xFF800000	F1	0xFF800000
F3	0x00000000	F3	0xFF800000

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


MIN.d F0, F4, F8

Before execution		After execution
F1:F0	0x000000000000000A	F1:F0	0x000000000000000A
F5:F4	0xC00000000000000C	F5:F4	0xC00000000000000C
F9:F8	0x00000000000000	F9:F8	0xC00000000000000C

FSR[7:0]	8'b00000000	FSR[7:0]	8'b01000000	(SUBO)


MINNM		Select the Signed Minimum of Fb and Fs [minmumNumber()]
Syntax:	{label:}	MINNM.s	Fb,	Fs,	Fd
		MINNM.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	IF (Fs) <= (Fb) THEN (Fs) → (Fd); ELSE THEN (Fb) → (Fd)
Status Affected:	SUBO, INVAL (see Note 1)
Exceptions Possible:	SUBO, INVAL
Encoding:	`1000`	`001P`	`zzdd`	`ddds`	`ssss`	`wwww`	`wUUU`	`1110`
Description:	Find the signed minimum of two floating-point values held in Fb and Fs. This instruction is compliant with the IEEE 754-2019 minimumNumber() operation. Compare the contents of the source registers Fb and Fs, then place the minimum of the two values in the destination register Fd. If Fb = Fs, Fd is loaded with the contents of Fs. This is a signed comparison operation (see note 3). If Fb = Fs (and of the same sign), Fd is loaded with the contents of Fs. When one of the input operands is a NaN and the other input is a floating-point number (that is not a NaN), the instructions will return the floating-point number. If both input operands are a NaN, the instructions will return a qNaN. The ‘P’ bit selects single (32-bit) or double precision (64-bit) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. Note: If not already set, the corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro. Operand value of -0 compares to less than +0.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1


MINNM.s F0, F1, F3

Before execution		After execution
F0	0x00000000	F0	0x00000000
F1	0x80000000	F1	0x80000000
F3	0x00000000	F3	0x80000000

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


MINNM.d F0, F4, F8

Before execution		After execution
F1:F0	0x800000000000000A	F1:F0	0x800000000000000A
F5:F4	0x3FF924920048245C	F5:F4	0x3FF924920048245C
F9:F8	0x00000000000000	F9:F8	0x800000000000000A

FSR[7:0]	8'b00000000	FSR[7:0]	8'b01000000	(SUBO)


MOV		Move Coprocessor Register to Wns with Signed Literal Offset
Syntax:	{label:}	MOV.l	Fs, [Wnd+Slit14]







Operands:	Wnd ∈ [W0 ... W15] Fs ∈ [F0 ... F31]
Operation:	Wns → [Wnd+Slit14]
Status Affected:	None
Encoding:	`1000`	`011s`	`ssss`	`dddd`	`kkkk`	`kkkk`	`kkkk`	`zz01`
Description:	Moves contents of the destination register to the source Effective Address. Syntax shown is for the floating-point coprocessor F-regs. The contents of Wnd are not modified by this operation. The instruction encoding includes space for a 12-bit literal which is scaled accordingly for long word data moves in order to generate the corresponding byte offset value. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘d’ bits select the floating-point destination register. Note: This instruction operates in Long Word mode only.
I-Words:	1
Cycles:	1


MOV		Move Fs to Fd
Syntax:	{label:}	MOV.s	Fs,	Fd
		MOV.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	Fs → Fd
Status Affected:	None
Exceptions Possible:	None
Encoding:	`1000`	`011P`	`zzdd`	`ddds`	`ssss`	`UUUU`	`UUUU`	`0010`
Description:	Move (copy) the contents of the source register Fs to the destination register Fd. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘d’ bits select the destination register. Note: Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1


MOV.s F0, F1

Before execution		After execution
F0	0x40C90FDB	F0	0x40C90FDB
F1	0x00000000	F1	0x40C90FDB


MOV.d F0, F2

Before execution		After execution
F1:F0	0x3FE62E42FEFA39EF	F1:F0	0x3FE62E42FEFA39EF
F3:F2	0x0000000000000000	F3:F2	0x3FE62E42FEFA39EF


MOVC		Move Constant Value to Fd
Syntax:	{label:}	MOVC.s index,		Fd
		MOVC.d


Operands (.s):	Fd ∈ [F0 ... F31]; index ∈ [0 ... 31]
Operands (.d):	Fd ∈ [F0, F2 ... F30]; index ∈ [0 ... 31]
Operation:	Constant table (index) → Fd
Status Affected:	None
Exceptions Possible:	None
Encoding:	`1000`	`011P`	`zzdd`	`dddU`	`UUUU`	`UUUk`	`kkkk`	`0110`
Description:	Move the constant value specified by the 5-bit index into the Fd register, as defined in the tables below. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘d’ bits select the destination register. The ‘k’ bits select the index. Note: Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1
Single Precision:
	Index	Data		Description
	31	32'H7FFF_FFFF		QNAN - RANGE ENDS
	30	32'H7FC0_0000		QNAN - RANGE STARTS
	29	32'H7FBF_FFFF		SNAN - RANGE ENDS
	28	32'H7F80_0001		SNAN - RANGE STARTS
	27	32'H7F80_0000		+INF
	26	32'H7F7F_FFFF		+MAX MAG NORMAL
	25	32'H0080_0000		+MIN MAG NORMAL
	24	32'H007F_FFFF		+MAX MAG SUB-NORMAL
	23	32'H0000_0001		+MIN MAG SUB-NORMAL
	22	32'H0000_0000		+0.0
	21	32'H8000_0000		-0.0
	20	32'H8000_0001		-MIN MAG SUB-NORMAL
	19	32'H807F_FFFF		-MAX MAG SUB-NORMAL
	18	32'H8080_0000		-MIN MAG NORMAL
	17	32'HFF7F_FFFF		-MAX MAG NORMAL
	16	32'HFF80_0000		-INF
	15	32'HFF80_0001		SNAN - RANGE STARTS
	14	32'HFFBF_FFFF		SNAN - RANGE ENDS
	13	32'HFFC0_0000		QNAN - RANGE STARTS
	12	32'HFFFF_FFFF		QNAN - RANGE ENDS
	11	32’H3F35_04F3		1/√ 2 =0.70710...
	10	32’H3FB5_04F3		√2 = 1.41421...
	9	32’H4054_9A78		LOG2(10) = 3.321
	8	32’H3F31_7218		LN(2) = 0.6931471 ...
	7	32’H402D_F854		E = 2.71828...
	6	32’H3F49_0FDB		Π/4 = 0.785398...
	5	32’H3FC9_0FDB		Π/2 = 1.5707...
	4	32'H4049_0FDB		Π = 3.14159...
	3	32’H40C9_0FDB		2Π = 6.283185...
	2	32'H4000_0000		2.0
	1	32'H3F80_0000		1.0
	0	32’H4120_0000		10.0
Double Precision:
	Index	Data			Description
	31	64'H7FFF_FFFF_FFFF_FFFF			QNAN - RANGE ENDS
	30	64'H7FF8_0000_0000_0000			QNAN RANGE STARTS
	29	64'H7FF7_FFFF_FFFF_FFFF			SNAN RANGE ENDS
	28	64'H7FF0_0000_0000_0001			SNAN RANGE STARTS
	27	64'H7FF0_0000_0000_0000			+INF
	26	64'H7FEF_FFFF_FFFF_FFFF			+MAX MAG NORMAL
	25	64'H0010_0000_0000_0000			+MIN MAG NORMAL
	24	64'H000F_FFFF_FFFF_FFFF			+MAX MAG SUB-NORMAL
	23	64'H0000_0000_0000_0001			+MIN MAG SUB-NORMAL
	22	64'H0000_0000_0000_0000			+0.0
	21	64'H8000_0000_0000_0000			-0.0
	20	64'H8000_0000_0000_0001			-MIN MAG SUB-NORMAL
	19	64'H800F_FFFF_FFFF_FFFF			-MAX MAG SUB-NORMAL
	18	64'H8010_0000_0000_0000			-MIN MAG NORMAL
	17	64'HFFEF_FFFF_FFFF_FFFF			-MAX MAG NORMAL
	16	64'HFFF0_0000_0000_0000			-INF
	15	64'HFFF0_0000_0000_0001			SNAN RANGE STARTS
	14	64'HFFF7_FFFF_FFFF_FFFF			SNAN RANGE ENDS
	13	64'HFFF8_0000_0000_0000			QNAN RANGE STARTS
	12	64'HFFFF_FFFF_FFFF_FFFF			QNAN RANGE ENDS
	11	64'H3FE6_A09E_667F_3BCD			1/√2=0.7071...
	10	64'H3FF6_A09E_667F_3BCD			√2=1.41421..
	9	64'H400A_934F_0979_A371			LOG2(10)= 3.321
	8	64'H3FE6_2E42_FEFA_39EF			LN(2)=0.69314
	7	64'H4005_BF0A_8B14_5769			E = 2.71828...
	6	64'H3FE9_21FB_5444_2D18			π/4= 0.7853...
	5	64'H3FF9_21FB_5444_2D18			π/2 = 1.5707..
	4	64'H4009_21FB_5444_2D18			π = 3.14159...
	3	64'H4019_21FB_5444_2D18			2π = 6.28...
	2	64'H4000_0000_0000_0000			2.0
	1	64'H3FF0_0000_0000_0000			1.0
	0	64'H4024_0000_0000_0000			10.0


MOVC.s #3, F0

Before execution		After execution
F0	0x00000000	F0	0x40C90FDB


MOVC.d #8, F0

Before execution		After execution
F1:F0	0x0000000000000000	F1:F0	0x3FE62E42FEFA39EF


MOV		Move Coprocessor Register to Wd
Syntax:	{label:}	MOV.l	Fs,	Wd
			FSR,	[Wd]
			FSRH,	[Wd++]
			FCR,	[Wd--]
			FEAR,	[--Wd]
				[++Wd]
				[Wd+Wb]


Operands:	Fs ∈ [F0 ... F31]; Wd ∈ [W0 ... W15]; Wb ∈ [W0 ... W14] (see Note 2)
Operation:	(Fs or FSR or FSRH or FCR or FEAR) → (EAd)
Status Affected:	None
Encoding:	`S000`	`011s`	`ssss`	`dddd`	`UUUq`	`qqww`	`wwRU`	`zz00`
Description:	Move the contents of the source coprocessor data, status or control register into the destination register. Syntax shown is for the floating-point coprocessor registers. The ‘S’ bit selects instruction size. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the coprocessor source register. The ‘d’ bits select the destination register. The ‘q’ bits select the destination addressing mode. The ‘w’ bits define the offset Wb. The ‘R’ bit selects between the F-regs and FPU special registers. Note: This instruction operates in Long Word mode only. Stack Pointer (W15) limit checks are only performed for Wd = W15. Consequently, setting Wb = W15 is not permitted.
I-Words:	1 or 0.5
Cycles:	1


MOV		Move Wns with Signed Literal Offset to Coprocessor Register
Syntax:	{label:}	MOV.l	[Wns+Slit14], Fd







Operands:	Wns ∈ [W0 ... W15] Fd ∈ [F0 ... F31]
Operation:	[Wns+Slit14] → Fd
Status Affected:	None
Encoding:	`1000`	`010d`	`dddd`	`ssss`	`kkkk`	`kkkk`	`kkkk`	`zz01`
Description:	Moves contents of the source Effective Address into the destination register. Syntax shown is for the floating-point coprocessor F-regs. The contents of Wns are not modified by this operation. The instruction encoding includes space for a 12-bit literal which is scaled accordingly for long word data moves in order to generate the corresponding byte offset value. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘d’ bits select the floating-point destination register. Note: This instruction only supported when a coprocessor is instantiated. This instruction operates in Long Word mode only.
I-Words:	1
Cycles:	1


MOV		Move Ws to Coprocessor Register
Syntax:	{label:}	MOV.l	Ws,	Fd
			[Ws],	FSR
			[Ws++]	FCR
			[Ws--]	FEAR
			[--Ws],
			[++Ws],
			[Ws+Wb],


Operands:	Fd ∈ [F0 ... F31]; Ws ∈ [W0 ... W15]; Wb ∈ [W0 ... W14] (see Note 2)
Operation:	(EAs) → Fd, FSR, FCR or FEAR
Status Affected:	None
Encoding:	`S000`	`010d`	`dddd`	`ssss`	`pppU`	`UUww`	`wwRU`	`zz00`
Description:	Move the contents of the source register into the coprocessor destination data, status or control register. Syntax shown is for the floating-point coprocessor registers. The ‘S’ bit selects instruction size. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘d’ bits select the coprocessor destination register. The ‘p’ bits select the source addressing mode. The ‘w’ bits define the offset Wb. The ‘R’ bit selects between the F-regs and FPU special registers. Note: This instruction operates in Long Word mode only. Stack Pointer (W15) limit checks are only performed for Wd = W15. Consequently, setting Wb = W15 is not permitted.
I-Words:	1 or 0.5
Cycles:	1


MOV		Move Long Literal to Coprocessor Register
Syntax:	{label:}	MOV.l	lit32,	Fd
				FSR
				FCR


Operands:	lit32 ∈ [0 ... 4GB]; Fd ∈ [F0 ... F31]
Operation:	lit32 → (Fd or FSR or FCR)
Status Affected:	None
Encoding:
1st word	`1000`	`001z`	`kkkk`	`kkkk`	`kkkk`	`kkkk`	`kkkk`	`z001`
2nd word	`1000`	`001d`	`dddd`	`Ukkk`	`kkkU`	`UUkk`	`kkkk`	`R101`
Description:	The literal ‘k’ is loaded into the coprocessor destination data register. Syntax shown is for the floating-point coprocessor register. The ‘d’ bits select the coprocessor destination register. The ‘z’ bits select the target coprocessor.  zz[1:0] = Word1[24], Word1[3] The ‘R’ bit selects between the F-regs and FPU special registers. The ‘k’ bits specify the value of the 32-bit literal: lit32[31:0] = Word1[18:13], Word2[9:4], Word1[23:4]
I-Words:	2
Cycles:	2


MUL		Floating-Point Signed Multiply
Syntax:	{label:}	MUL.s	Fb,	Fs,	Fd
		MUL.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	(Fb) * (Fs) → Fd;
Status Affected:	SUBO, INX, UDF, OVF, INVAL (see Note 1)
Exceptions Possible:	SUBO, INX, UDF, OVF, INVAL
Encoding:	`1000`	`010P`	`zzdd`	`ddds`	`ssss`	`wwww`	`wUUU`	`0110`
Description:	Multiply the signed contents of the source register Fb with the signed contents of the source register Fs, then write the product to Fd. (0 * ∞) or (∞ * 0) will result in distinguished qNaN and signal an INVAL exception. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. Note: If not already set, the corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	3
DP Execute Cycles:	3
Repetition Rate:	1


MUL.s F0, F1, F3

Before execution		After execution
F0	0x41200000	F0	0x41200000
F1	0x41C80000	F1	0x41C80000
F3	0x00000000	F3	0x437A0000

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


MUL.d F0, F2, F6

Before execution		After execution
F1:F0	0xFFE0000000000030	F1:F0	0xFFE0000000000030
F3:F2	0xFFE0000000000030	F3:F2	0xFFE0000000000030
F7:F6	0x00000000000000	F7:F6	0x7FEFFFFFFFFFFFFF

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00010100	(OVF, INX)


NEG		Negate Fs
Syntax:	{label:}	NEG.s	Fs,	Fd
		NEG.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	-Fs → Fd
Status Affected:	SUBO¹
Exceptions Possible:	SUBO
Encoding:	`1000`	`100P`	`zzdd`	`ddds`	`ssss`	`UUUU`	`UUUU`	`0110`
Description:	Negate the sign of the contents of the source register Fs and place the result in the destination register Fd. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘`s`’ bits select the source register. The ‘d’ bits select the destination register. Note: If not already set, the corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1

Note: This instruction only affects the sign bit and will not quit an sNaN input operand.


NEG.s F0, F3

Before execution		After execution
F0	0x40800001	F0	0x40800001
F3	0x00000000	F3	0xC0800001

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


NEG.d F0, F2

Before execution		After execution
F1:F0	0x8000000000000001	F1:F0	0x8000000000000001
F3:F2	0x0000000000000000	F3:F2	0x0000000000000001

FSR[7:0]	8'b00000000	FSR[7:0]	8'b01000000	(SUBO)


POP		Pop FPU Coprocessor Register
Syntax:	{label:}	POP.l	Fd
			FSR
			FCR
			FEAR


Operands:	Fd ∈ [F0 ... F31]
Operation:	(W15)-4 → W15 (TOS) → (Fd or FSR or FCR or FEAR)
Status Affected:	None
Encoding:	`0010`	`111d`	`dddd`	`zzRU`
Description:	Move the top of system stack to the coprocessor destination register. Use of the system Stack Pointer ([--W15]) is implied. Syntax shown is for the floating-point coprocessor registers. The ‘d’ bits select the floating point destination register. The ‘z’ bits select the target coprocessor. The ‘R’ bit selects between the F-regs and FPU special registers. Note: This instruction operates in Long Word mode only. FSRH not supported as it would clear exception status in FSR[15:0].
Words:	1
Cycles:	1


PUSH		Push FPU Coprocessor Register
Syntax:	{label:}	PUSH.l	Fs
			FSR
			FSRH
			FCR
			FEAR


Operands:	Fs ∈ [F0 ... F31]
Operation:	(Fs or FSR or FSRH or FCR or FEAR) → (TOS) (W15)+4 → W15
Status Affected:	None
Encoding:	`0010`	`011s`	`ssss`	`zzRU`
Description:	Move the contents of the source floating point register to the top of system stack. Use of the system Stack Pointer ([W15++]) is implied. Syntax shown is for the floating-point coprocessor registers. When FSRH is selected, long word value {FSR[31:16], 16’b0} will be pushed onto the stack. FSR[31:16] comprises of FCPS/FCPQ and FTST instruction status only. The ‘s’ bits select the floating point source register. The ‘z’ bits select the target coprocessor. The ‘R’ bit selects between the F-regs and FPU special registers. Note: This instruction operates in Long Word mode only.
Words:	0.5
Cycles:	1


SIN		Evaluate the Sine of Fs
Syntax:	{label:}	SIN.s	Fs,	Fd



Operands (.s):	Fs ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operation:	Sin(Fs) → Fd
Status Affected:	SUBO, INX, UDF, INVAL (see Note 1)
Exceptions Possible:	SUBO, INX, UDF, INVAL
Encoding:	`1000`	`110P`	`zzdd`	`ddds`	`ssss`	`UUUU`	`UUUU`	`0010`
Description:	Calculate the sine of contents of the source register Fs  (where Fs = [2πk + θ rads]), and place the result in the destination register Fd. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register The ‘d’ bits select the destination register. Note: If not already set, the corresponding sticky exception status will also be set. This operation is only supported using single precision floating-point. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	4
Repetition Rate:	1


SIN.s F0, F3

Before execution		After execution
F0	0x3F492492	F0	0x3F492492
F3	0x00000000	F3	0x3F351398

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


SIN.s F0, F3

Before execution		After execution
F0	0x7F800000	F0	0x7F800000
F3	0x00000000	F3	0x7FC00001	(distinguished qNaN)

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000001	(INVAL)


SQRT		Square Root Fs, result in Fd
Syntax:	{label:}	SQRT.s	Fs,	Fd
		SQRT.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	√Fs → Fd
Status Affected:	SUBO, INX, INVAL (see Note 1)
Exceptions Possible:	SUBO, INX, INVAL
Encoding:	`1000`	`100P`	`zzdd`	`ddds`	`ssss`	`UUUU`	`UUUU`	`1010`
Description:	Take the square root of contents of the source register Fs, and place the result in the destination register Fd. If Fs < 0, destination will be written with distinguished qNaN and signal an FPU INVAL exception. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘`s`’ bits select the source register. The ‘d’ bits select the destination register. Note: If not already set, the corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	10
DP Execute Cycles:	13
Repetition Rate:	TBD


SQRT.s F0, F3

Before execution		After execution
F0	0x00000030	F0	0x00000030
F3	0x00000000	F3	0x1B9CC470

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


SQRT.d F0, F2

Before execution		After execution
F1:F0	0x4050000000000000	F1:F0	0x4050000000000000
F3:F2	0x0000000000000000	F3:F2	0x4020000000000000

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00010000	(INX)


SUB		Subtract Fs from Fb
Syntax:	{label:}	SUB.s	Fb,	Fs,	Fd
		SUB.d


Operands (.s):	Fs ∈ [F0 ... F31]; Fb ∈ [F0 ... F31]; Fd ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]; Fb ∈ [F0, F2 ... F30]; Fd ∈ [F0, F2 ... F30]
Operation:	Fb - Fs → Fd
Status Affected:	SUBO, INX, UDF, OVF, INVAL (see Note 1)
Exceptions Possible:	SUBO, INX, UDF, OVF, INVAL
Encoding:	`1000`	`000P`	`zzdd`	`ddds`	`ssss`	`wwww`	`wUUU`	`0110`
Description:	Subtract the contents of the source register Fs from the contents of the base register Fb, then place the result in the destination register Fd. (∞ - ∞) will result in distinguished qNaN and signal an FPU INVAL exception. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. The ‘w’ bits select the base register. The ‘d’ bits select the destination register. Note: If not already set, the corresponding sticky exception status will also be set. Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	2
DP Execute Cycles:	2
Repetition Rate:	1


SUB.s F0, F1, F3

Before execution		After execution
F0	0x40800001	F0	0x40800001
F1	0xC0F800F1	F1	0xC0F800F1
F3	0x00000000	F3	0xC07001E0

FSR[7:0]	8'b00000000	FSR[7:0]	8'b00000000


SUB.d F0, F2, F6

Before execution		After execution
F1:F0	0x000FFFFFFFFFFFFF	F1:F0	0x000FFFFFFFFFFFFF
F3:F2	0x000FFFFFFFFFFFFF	F3:F2	0x000FFFFFFFFFFFFF
F7:F6	0x001FFFFFFFFFFFFE	F7:F6	0x001FFFFFFFFFFFFE

FSR[7:0]	8'b00000000	FSR[7:0]	8'b01000000	(SUBO)


TST		Test Fs
Syntax:	{label:}	TST.s	Fs
		TST.d


Operands (.s):	Fs ∈ [F0 ... F31]
Operands (.d):	Fs ∈ [F0, F2 ... F30]
Operation:	If Fs is +/-Subnormal FSR.SUB = 1 else FSR.SUB = 0 If Fs is +/- Infinity FSR.INF = 1 else FSR.INF = 0 If Fs is Negative FSR.FN = 1 else FSR.FN = 0 If Fs is +/- Zero FSR.FZ = 1 else FSR.FZ = 0 If Fs is qNaN or sNaN FSR.FNAN = 1 else FSR.FNAN = 0
Status Affected:	SUB, INF, FN, FZ, FNAN
Exceptions Possible:	None
Encoding:	`1001`	`010P`	`zzUU`	`UUUs`	`ssss`	`UUUU`	`UUUU`	`0010`
Description:	Inspect the contents of Fs and set the FSR status accordingly. The ‘P’ bit selects single (.s) or double precision (.d) operation. The ‘z’ bits select the target coprocessor. The ‘s’ bits select the source register. Note: Coprocessor select bit field zz = 2’b00 for floating-point coprocessor macro.
I-Words:	1
SP Execute Cycles:	1
DP Execute Cycles:	1
Repetition Rate:	1


TST.s F0

Before execution		After execution
F0	0xFFC0000A	F0	0xFFC0000A
	(a -ve NaN number)
FSR[31:24]	8'b00000000	FSR[31:24]	8'b00000101	(FN, NAN)


TST.d F0

Before execution		After execution
F1:F0	0xFFF0000000000000	F1:F0	0xFFF0000000000000
	(a -ve Inf number)
FSR[31:24]	8'b00000000	FSR[31:24]	8'b00001100	(FN, INF)