4.8 FPU Instruction Encoding and Opcode Field Description

Table 4-11. Symbols Used in FPU Instruction Encoding Field Description
FieldDescription
lit1616-bit unsigned literal Î {0...65535}
indexLiteral address index into 32 entry SP and DP constant tables
.s32-bit Single Precision selection
.d64-bit Double Precision selection
FdOne of 32 destination floating-point registers Î {F0..F31} (Register Direct)
FbOne of 32 source floating-point registers Î {F0..F31} (Register Direct)
FsOne of 32 source floating-point registers Î {F0..F31} (Register Direct)

SUB, INF, FN, FZ, FNAN

GT, LT, EQ, UN

SUBO, HUGI, INX, UDF, OVF,

DIV0, INVAL

FPU status bits (FSR)

Note: Flags for exceptions that cannot be signaled by an instruction are always cleared by that instruction (sticky flags are unaffected)
Table 4-12. FPU Instruction Opcode Field Descriptions
FieldDescription
PSelects Single Precision (P=0) or Double Precision (P=1) operation
RSelects between FPU coprocessor special registers (R=1) or F-regs (R=0)
UUnused (don’t care) instruction bit. Assembler to assign ‘0’
ddddd

R=0: FPU coprocessor Fd destination register select: 00000=F0; 11111=F31

R=1: FPU coprocessor special register select

eeeFPU rounding mode selection
kkkk kkkk kkkk kkkk16-bit literal field, constant data
sssss

R=0: FPU coprocessor Fs source register select: 00000=F0; 11111=F31

R=1: FPU coprocessor special register select