4.6 Instruction Descriptions (E to MULUU)

Word mode: kx ∈ {-8, -6, -4, -2, 2, 4, 6, 8};
 ky ∈ {-8, -6, -4, -2, 2, 4, 6, 8};

Long Word mode: kx ∈ {-16, -12, -8, -4, 4, 8, 12, 16};
 ky ∈ {-16, -12, -8, -4, 4, 8, 12, 16};

AWB ∈ {W0, W1, W2, W3, W13, [W13++], [W15++]⁴}

(ACC(B or A)) rounded → AWB

When Indirect Pre/Post Modified Addressing:

(Wx)+kx→Wx or (Wx)-kx→Wx;

(Wy)+ky→Wy or (Wy)-ky→Wy;

When indirect addressing is selected for either or both X and Y address space, the Wx and Wy registers provide the corresponding indirect addresses. The address modifier values are kx and ky, respectively, and represent the number of data bytes by which to modify the Effective Address.

The optional AWB specifies the direct or indirect (see note 4) store of the (32-bit) rounded fractional contents of the accumulator not targeted by the ED operation. Rounding mode is defined by CORCON.RND. Write data width is determined by selected instruction data size (see note 5). AWB is not intended for use when the DSP engine is operating in Integer mode.

Data read may be 16-bit or 32-bit values. All indirect address modification is scaled accordingly.

The ‘L’ bit selects word or long word operation.

The ‘A’ bit selects the accumulator for the result.

The ‘I’ bits select the Operation.X-Space Addressing mode.

The ‘i’ bits select the kx modification value.

The ‘J’ bits select the Operation.Y-Space Addressing mode.

The ‘j’ bits select the ky modification value.

The ‘s’ bits select the Wx register

The ‘w’ bits select the Wy register.

The ‘a’ bits select the accumulator write-back destination and addressing mode.

Word mode: kx ∈ {-8, -6, -4, -2, 2, 4, 6, 8};
 ky ∈ {-8, -6, -4, -2, 2, 4, 6, 8};

Long Word mode: kx ∈ {-16, -12, -8, -4, 4, 8, 12, 16};
 ky ∈ {-16, -12, -8, -4, 4, 8, 12, 16};

AWB ∈ {W0, W1, W2, W3, W13, [W13++], [W15++]⁴}

(ACC(B or A)) rounded → AWB

When Indirect Pre/Post Modification Addressing:

(Wx)+kx→Wx or (Wx)-kx→Wx;

(Wy)+ky→Wy or (Wy)-ky→Wy;

When indirect addressing is selected for either or both X and Y address space, the Wx and Wy registers provide the corresponding indirect addresses. The address modifier values are kx and ky, respectively, and represent the number of data words by which to modify the Effective Address.

The optional AWB specifies the direct or indirect (see note 4) store of the (32-bit) rounded fractional contents of the accumulator not targeted by the EDAC operation. Rounding mode is defined by CORCON.RND. Write data width is determined by selected instruction data size (see note 5). AWB is not intended for use when the DSP engine is operating in Integer mode.

Data read may be 16-bit or 32-bit values. All indirect address modification is scaled accordingly.

The ‘L’ bit selects word or long word operation.

The ‘A’ bit selects the accumulator for the result.

The ‘I’ bits select the Operation.X-Space Addressing mode.

The ‘i’ bits select the kx modification value.

The ‘J’ bits select the Operation.Y-Space Addressing mode.

The ‘j’ bits select the ky modification value.

The ‘s’ bits select the Wx register.

The ‘w’ bits select the Wy register.

The ‘a’ bits select the accumulator write-back destination and addressing mode.

The ‘s’ bits select the Wns register.

The ‘d’ bits select the Wnd register.

The next MSb after the Sign bit is assigned number zero. For a word operation, the LSb number is assigned -14 and a result of -15 (C=1) indicates that the bit was not found. For a long word operation, the LSb number is assigned -30 and a result of -31 (C=1) indicates that the bit was not found.

C is cleared for all non-zero results.


The ‘L’ bit selects word or long word operation.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

See and for modifier addressing information.

The MSb is assigned number one. For a word operation, the LSb number is assigned 16, and a result of zero (C=1) indicates that the bit was not found. For a long word operation, the LSb number is assigned 32 and a result of zero (C=1) indicates that the bit was not found.

C is cleared for all non-zero results.

The ‘L’ bit selects word or long word operation.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The LSb is assigned number one. For a word operation, the MSb number is assigned 16, and a result of zero (C=1) indicates that the bit was not found. For a long word operation, the MSb number is assigned 32 and a result of zero (C=1) indicates that the bit was not found.

C is cleared for all non-zero results.

The ‘L’ bit selects word or long word operation.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

0→ Z; 0→ N; 0→ OV

}

ELSE IF (Ws) < (Wb+1) THEN {
 (Wb+1) → Ws;

0→ Z; 1→ N; 0→ OV
}
ELSE {
 (Ws) → Ws⁴;

1→ Z; 0→ N; 0→ OV

}

For long word data size, if Ws[31:0] is greater than Wb[31:0], set Ws[31:0] to the limit value held in Wb[31:0]. For word data sizes, if Ws[15:0] is greater than Wb[15:0], set Ws[15:0] to the limit value held in Wb[15:0] (Ws[31:16] is ignored). The Z, N and OV status bits are updated such that a subsequent BGT instruction will take a branch.

For long word data size, if Ws[31:0] is less than Wb+1[31:0], set Ws[31:0] to the limit value held in Wb+1[31:0]. For word data sizes, if Ws[15:0] is less than Wb+1[15:0], set Ws[15:0] to the limit value held in Wb+1[15:0] (Ws[31:16] is ignored). The Z, N and OV status bits are updated such that a subsequent BLT instruction will take a branch.

If Ws[31:0] is less than or equal to the maximum limit value in Wb[31:0], and greater than or equal to the minimum limit value in Wb+1[31:0] (for long word sized data), or Ws[15:0] is less than or equal to the maximum limit value in Wb[15:0] and greater than or equal to the minimum limit value in Wb+1[15:0] (for word sized data), neither data limit is applied such that the contents of Ws will not change (for the given data size). The Z status bit is set such that a subsequent BZ instruction will take a branch (OV and N status are both cleared).

For word sized register direct operations, Ws is always 0 extended to 32-bits (even if neither of the data limits are applied)⁴.

Note that the instruction always executes the maximum compare first. Should Ws be less than the maximum, it will then execute the minumum compare, and if Ws is found to be not less than the minimum, Ws will remain unchanged.

Furthermore, should the (maximum) limit value Wb be inadvertently set to less than or equal to the (minimum) limit value Wb+1, the same compare sequence will still be executed. This condition is not detected.

The OV status bit is always cleared by this instruction.

The ‘s’ bits select the source (data value) register.

The ‘w’ bits select the base (data limit) register.

The ‘p’ bits select the source addressing mode.

0→ Z; 0→ N; 0→ OV;

)

ELSE IF (Ws) < (Wb+1) THEN (
 IF FLIM.v THEN (Ws) - (Wb+1) → Wnd
 ELSE -1 → Wnd;
 (Wb+1) → Ws;

0→ Z; 1→ N; 0→ OV;
)
ELSE (

0 → Wnd;

(Ws) → Ws⁴;

1→ Z; 0→ N; 0→ OV;

)

For long word data size, if Ws[31:0] is greater than Wb[31:0], set Ws[31:0] to the limit value held in Wb[31:0]. For word data sizes, if Ws[15:0] is greater than Wb[15:0], set Ws[15:0] to the limit value held in Wb[15:0] (Ws[31:16] is ignored).

In all cases, write the (signed) value by which the limit is exceeded to Wnd[31:0] (FLIM.v, where opcode bit field V = 1) or set Wnd to +1 (FLIM, where opcode bit field V = 0). Whenever Ws is greater than Wb, Wnd will always be a positive value. The Z, N and OV status bits are updated such that a subsequent BGT instruction will take a branch.

For long word data size, if Ws[31:0] is less than Wb+1[31:0], set Ws[31:0] to the limit value held in Wb+1[31:0]. For word data sizes, if Ws[15:0] is less than Wb+1[15:0], set Ws[15:0] to the limit value held in Wb+1[15:0] (Ws[31:16] is ignored). In all cases, write the (signed) value by which the limit is exceeded to Wnd[31:0] (FLIM.v, where opcode bit field V = 1) or set Wnd to +1 (FLIM, where opcode bit field V = 0). Whenever Ws is less than Wb+1, Wnd will always be a negative value. The Z, N and OV status bits are updated such that a subsequent BLT instruction will take a branch.

For word sized register direct operations, Ws is always zero extended to 32-bits (even if neither of the data limits are applied)⁴.

Note that the instruction always executes the maximum compare first. Should Ws be less than the maximum, it will then execute the minimum compare, and if Ws is found to be not less than the minimum, Ws will remain unchanged.
Furthermore, should the (maximum) limit value Wb be inadvertently set to less than or equal to the (minimum) limit value Wb+1, the same compare sequence will still be executed. This condition is not detected.

The OV status bit is always cleared by this instruction.

The ‘s’ bits select the source (data value) register.

The ‘w’ bits select the base (data limit) register.

The ‘d’ bits select the destination (limit test result) register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

The ‘V’ bit selects the result format for Wnd.

See for modifier addressing information.

The ‘n’ bits form the target address.

NOP → Instruction Register.

The Wns[23:0] is loaded into PC[23:0]. Wns must therefore contain a PS byte address.

The value of Wns[0] is ignored and PC[0] is always set to 1’b0.


GOTO is a two-cycle instruction.

The ‘s’ bits select the source register.

If Wns[31:24] !=8’h00, an address error trap will be initiated.

The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘d bits select the Working register.

The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘d’ bits select the Working register.

The ‘S’ bit selects instruction size.

The ‘L’ and ‘B’ bits select operation data width.

The ‘s’ bits select the source register.

The ‘w’ bits select the base register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

Note: The literal is zero-extended to the selected data size of the operation

The ‘L’ and ‘B’ bits select operation data width.

The ‘k’ bits provide the literal operand (MSb in op[2]).

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

See and for modifier addressing information.

The ‘L’ and ‘B’ bits select operation data width.

The ‘s’ bits select the Working register.

The ‘k’ bits specify the literal operand.

The ‘T’ bit selects between Ws (T = 0) and SR (T = 1) target registers.

The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘s’ bits select the Working register.

8{Ws[15]}, Ws[15:0], 48’h000000000000 → ACC[71:0]

Shift_Slit6(ACC) → ACC

For Long Word operation:

8{Ws[31]}, Ws[31:0], 32’h00000000 → ACC[71:0]

Shift_Slit6(ACC) → ACC

For a word operation (LAC{.w}), the value contained at the Effective Address is assumed to be Q1.15 signed fractional data and is written into ACCx[63:48]. ACCx[47:0] is set to all 0’s, and ACCx[63:0] is automatically sign-extended (through bit 71). The accumulator is then arithmetically shifted by the value held in slit6.

For a long word operation (LAC.l), the value contained at the Effective Address is assumed to be Q1.31 signed fractional data and is written into ACCx[63:32]. ACCx[31:0] is set to all 0’s, and ACCx[63:0] is automatically sign-extended (through bit 71). The accumulator is then arithmetically shifted by the value held in slit6.


The ‘L’ bit selects word or long word operation.

The ‘A’ bits specify the destination accumulator.

The ‘s’ bits specify the source register Wns.

The ‘p’ bits select the source addressing mode.

The ‘w’ bits specify the offset register Wb.

The ‘k’ bits encode the optional operand Slit6 which determines the amount of the accumulator shift; if the operand Slit6 is absent, the literal bit field is set to all 0’s.

Shift_Slit6(ACC) → ACC

The ‘A’ bits specify the destination accumulator.

The ‘s’ bits specify the source register Wns.

The ‘p’ bits select the source addressing mode.

The ‘w’ bits specify the offset register Wb.

The ‘k’ bits encode the optional operand Slit6 which determines the amount of the accumulator shift; if the operand Slit6 is absent, the literal bit field is set to all 0’s.

(W15) + 4 → W15

(W15) → W14;

(W15) + lit16 → W15

The ‘k’ bits specify the size of the stack frame in bytes.

(W15) + 4 → W15

(W15) → W14;

(W15) + lit5, 2’b00 → W15

The ‘k’ bits specify the size of the stack frame (in long words).

0 → Wd[31], (Ws[31:1]) → Wd[30:0], (Ws[0]) → C

For word operation:

0 → Wd[15], (Ws[15:1]) → Wd[14:0], (Ws[0]) → C

For byte operation:

0 → Wd[7], (Ws[7:1]) → Wd[6:0], (Ws[0]) → C

Destination register direct Extended Byte or Word mode will zero-extend the result to 32-bits, then write to Wd.

The ‘S’ bit selects instruction size.

The ‘L’ and ‘B’ bits select operation data width.


The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

0 → Dest[7:1], (f[7:1]) → Dest[6:0], (f[0]) → C


For word operation:

0 → Dest[15], (f[15:1]) → Dest[14:0], (f[0]) → C

For long word operation:
 0 → Dest[31], (f[31:1]) → Dest[30:0], (f[0]) → C


The ‘L’ and ‘B’ bits select operation data width.

The ‘D’ bit selects the destination.

The ‘f’ bits select the address of the file register.

The ‘d’ bits select the Working register.

1’b0 → Right shift input (logical shift)

For long word operation:

Ws[31:0], 32’b0 → Shift_In[63:0]

Logical shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[63:32] → Wd

For word operation:

16’b0,Ws[15:0],32’b0 → Shift_In[63:0]

Logical shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[47:32] → Wd[15:0]

The N flag is always cleared unless the shift value is zero (see note 1).

This instruction will generate the correct result for any shift value in lit5 (a word operation shift value > 15, Wd[15:0]=0x0000).

Register Direct Word mode will zero-extend the result to 32-bits, then write to Wd.

The ‘S’ bit selects instruction size.

The ‘L’ bit selects word or long word operation.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘q’ bits select the destination addressing mode.

The ‘k’ bits provide the literal operand.

For long word operation:

Ws[31:0], 32’b0 → Shift_In[63:0]

Logical shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[63:32] → Wd

For word operation:

16’b0,Ws[15:0],32’b0 → Shift_In[63:0]

Logical shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[47:32] → Wd[15:0]

For byte operation:

24’b0,Ws[7:0],32’b0 → Shift_In[63:0]

Logical shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[39:32] → Wd[7:0]

When used in isolation, this instruction will generate the correct result for any shift value in Wb[15:0]:

• For a byte operation shift value > 7, Wd[7:0]=0x00
• For a word operation shift value > 15, Wd[15:0]=0x0000
• For a long word operation shift value > 31, Wd=0x00000000

  When used in conjunction with ASRMW and/or LSRMW instructions for multi-precision multi-bit shift operations, this instruction will not generate a correct result for any shift value greater than 32.

  Any data held in Wb[31:16] will have no effect.

  The N flag is always cleared unless the shift value is 0 (see note 1).

  Destination register direct Extended Byte or Word mode will zero-extend the result to 32-bits, then write to Wd.

  The ‘L’ and ‘B’ bits select operation data width.


  The ‘s’ bits select the source register.

  The ‘w’ bits select the base (shift count) register.

  The ‘d’ bits select the destination register.

  The ‘p’ bits select the source addressing mode.

  The ‘q’ bits select the destination addressing mode.

  Note:

  1. The N flag can only be set if the MSb of Ws = 1 with a shift value of zero.

0 → Right shift input (logical shift)

Ws[31:0], 32’b0 → Shift_In[63:0]

Logical shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[63:32] → Wnd

Shift_Out[31:0] | Wnd-1 → Wnd-1

The Z bit is “sticky” (can only be cleared).

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

The ‘k’ bits provide the literal operand.

0 → Right shift input (logical shift)

Ws[31:0], 32’b0 → Shift_In[63:0]

Logical shift right Shift_In[63:0] by Shift_Val → Shift_Out[63:0]

Shift_Out[63:32] → Wnd

Shift_Out[31:0] | Wnd-1 → Wnd-1

The right shift may be by any amount between zero and 32 bits. Should the shift value held in Wb[15:0] exceed 2’d32, the shift value will saturate to 2’d32 for consistency. Any data held in Wb[31:16] will have no effect.

The Z bit is “sticky” (can only be cleared).

The ‘w’ bits select the base (shift count) register.

The ‘s’ bits select the source register.

The ‘d’ bits select the destination register.

The ‘p’ bits select the source addressing mode.

Shift_Slit6(ACC) → ACC

The ‘A’ bits specify the destination accumulator.

The ‘s’ bits specify the source register Wns.

The ‘p’ bits select the source addressing mode.

The ‘w’ bits specify the offset register Wb.

The ‘k’ bits encode the optional operand Slit6 which determines the amount of the accumulator shift; if the operand Slit6 is absent, the literal bit field is set to all 0’s.

Word mode: kx ∈ {-8, -6, -4, -2, 2, 4, 6, 8};
 ky ∈ {-8, -6, -4, -2, 2, 4, 6, 8};

Long Word mode: kx ∈ {-16, -12, -8, -4, 4, 8, 12, 16};
 ky ∈ {-16, -12, -8, -4, 4, 8, 12, 16};

AWB ∈ {W0, W1, W2, W3, W13, [W13++], [W15++]³}

(ACC(B or A)) rounded → AWB

When Indirect Pre/Post Modified Addressing:

(Wx)+kx→Wx or (Wx)-kx→Wx;

(Wy)+ky→Wy or (Wy)-ky→Wy;

When indirect addressing is selected for either or both the X and Y address space, Wx and Wy registers provide the corresponding indirect addresses. The address modifier values are kx and ky, respectively, and represent the number of data bytes by which to modify the Effective Address.

The optional AWB specifies the direct or indirect (see note 4) store of the (32-bit) rounded fractional contents of the accumulator not targeted by the MAC operation. Rounding mode is defined by CORCON.RND. Write data width is determined by selected instruction data size. AWB is not intended for use when the DSP engine is operating in Integer mode.

Data read may be 16-bit or 32-bit values. All indirect address modification is scaled accordingly.

The ‘L’ bit selects word or long word operation.

The ‘A’ bit selects the accumulator for the result.

The ‘I’ bits select the Operation.X-Space Addressing mode.

The ‘i’ bits select the kx modification value.

The ‘J’ bits select the Operation.Y-Space Addressing mode.

The ‘j’ bits select the ky modification value.

The ‘s’ bits select the Wx register

The ‘w’ bits select the Wy register.

The ‘a’ bits select the accumulator write-back destination and addressing mode.

0→ Z; 0→ N; 0→ OV

}

ELSE {

1→ Z; 0→ N; 0→ OV

}

For long word data size, if Ws[31:0] is greater than Wb[31:0], set Ws[31:0] to the limit value held in Wb[31:0]. For word data sizes, if Ws[15:0] is greater than Wb[15:0], set Ws[15:0] to the limit value held in Wb[15:0] (Ws[31:16] is ignored). The Z, N and OV status bits are set such that a subsequent BGT instruction will take a branch.

If Ws[31:0] is less than or equal to the maximum limit value in Wb[31:0] (for long word data size), or if Ws[15:0] is less than or equal to the maximum limit value in Wb[15:0] (word data size), the data limit is not applied such that contents of Ws will not change (for the given data size). The Z, N and OV status bits are set such that a subsequent BZ or BLE instruction will take a branch.

The OV status bit is always cleared by this instruction.

The ‘s’ bits select the source (data value) register.

The ‘w’ bits select the base (data limit) register.

The ‘p’ bits select the source addressing mode.

IF ACCA - ACCB > 0 THEN (

ACCB → ACCA;
 0→ Z; 0→ N; 0→ OV;

)

ELSE (

1→ Z; 0→ N; 0→ OV;
 )

)

IF (MAX B) THEN (

IF ACCB - ACCA > 0 THEN (
 ACCA → ACCB;

0→ Z; 0→ N; 0→ OV;

)

ELSE (

1→ Z; 0→ N; 0→ OV;
 )

)

The compare examines the full 72-bit value of the target accumulator and will therefore clamp an overflowed accumulator (variable saturation).

If the target accumulator is greater than the limit accumulator, load the target accumulator with the contents of the limit accumulator. The Z and N status bits are set such that a subsequent BGT instruction will take a branch.

If the target accumulator is not greater than the limit accumulator, the target accumulator is unaffected. The Z status bit is set such that a subsequent BZ instruction will take a branch.

The OV status bit is always cleared by this instruction.

The ‘A’ bit specifies the destination accumulator.

IF ACCA - ACCB > 0 THEN (

+1 → Wd OR ACCA - ACCB → Wd (see text);
 ACCB → ACCA;
 0→ Z; 0→ N; 0→ OV;

)

ELSE (

0 → Wd;

1→ Z; 0→ N; 0→ OV;
 )

)

IF (MAX B) THEN (

IF ACCB - ACCA > 0 THEN (
 +1 → Wd OR ACCB - ACCA → Wd (see text);

ACCA → ACCB;

0→ Z; 0→ N; 0→ OV;

)

ELSE (

0→ Wd;

1→ Z; 0→ N; 0→ OV;
 )

)

The compare examines the full 72-bit value of the target accumulator and will therefore clamp an overflowed accumulator (variable saturation).

If the target accumulator is greater than the limit accumulator, load the target accumulator with the contents of the limit accumulator. For MAX (instruction bit field V = 0, default when not declared), set Wd to +1. For MAX.v (instruction bit field V = 1), write the (signed) value by which the limit is exceeded to Wd:

- Word operation: Consider only bits [47:32] of the compare result and write to Wd (destination is also word-sized, see note 3). If the limit is exceeded by a value greater than that which can be represented by a signed 16-bit number, saturate the Wd write to the maximum 16-bit positive value (i.e., set Wd[15:0] to 0x7FFF).
- Long word operation: Consider only bits [31:0] of the compare result and write to Wd. If the limit is exceeded by a value greater than that which can be represented by a signed 32-bit number, saturate the Wd write to the maximum positive value (i.e., set Wd to 0x7FFFFFFF).

The Z and N status bits are set such that a subsequent BGT instruction will take a branch if the limit is exceeded.

If the target accumulator is not greater than the limit accumulator, the target accumulator is unaffected, and Wd is cleared. The Z status bit is set such that a subsequent BZ instruction will take a branch.

The OV status bit is always cleared by this instruction.

The ‘L’ bit selects word or long word operation.

The ‘A’ bit specifies the destination accumulator.

The ‘d’ bits select the destination register.

The ‘q’ bits select the destination addressing mode.

The ‘w’ bits define the offset Wb.

The ‘V’ bit defines the presence and result format for Wd.

0→ Z; 1→ N; 0→ OV

}

ELSE {

1→ Z; 0→ N; 0→ OV

}

For long word data size, if Ws[31:0] is less than Wb[31:0], set Ws[31:0] to the limit value held in Wb[31:0]. For word data sizes, if Ws[15:0] is less than Wb[15:0], set Ws[15:0] to the limit value held in Wb[15:0] (Ws[31:16] is ignored). The Z, N and OV status bits are set such that a subsequent BLT instruction will take a branch.

If Ws[31:0] is greater than or equal to the minimum limit value in Wb[31:0] (for long word data size), or if Ws[15:0] is greater than or equal to the minimum limit value in Wb[15:0] (word data size), the data limit is not applied such that contents of Ws will not change (for the given data size). The Z, N and OV status bits are set such that a subsequent BZ or BGE instruction will take a branch.

For word sized register direct operations, Ws is always zero extended to 32-bits (even if greater than or equal to the limit value in Wb)².

The OV status bit is always cleared by this instruction.

The ‘s’ bits select the source (data value) register.

The ‘w’ bits select the base (data limit) register.

The ‘p’ bits select the source addressing mode.

IF ACCA - ACCB < 0 THEN (

ACCB → ACCA;
 0→ Z; 1→ N; 0→ OV;

)

ELSE (

1→ Z; 0→ N; 0→ OV;
 )
)

IF (MIN B) THEN (

IF ACCB - ACCA < 0 THEN (

ACCA→ ACCB;

0→ Z; 1→ N; 0→ OV;

)

ELSE (

1→ Z; 0→ N; 0→ OV;

)

)

The compare examines the full 72-bit value of the target accumulator and will therefore clamp an overflowed accumulator (variable saturation).

If the target accumulator is less than the limit accumulator, load the target accumulator with the contents of the limit accumulator. The Z and N status bits are set such that a subsequent BLT instruction will take a branch.

If the target accumulator is not less than the limit accumulator, the target accumulator is unaffected. The Z status bit is set (Z = 1) such that a subsequent BLT instruction will take a branch.

The OV status bit is always cleared by this instruction.

The ‘A’ bit specifies the destination accumulator.

IF ACCA - ACCB < 0 THEN (

-1 → Wd OR ACCA - ACCB → Wd (see text);
 ACCB→ ACCA;
 0→ Z; 1→ N; 0→ OV;

)

ELSE (

0→ Wd;

1→ Z; 0→ N; 0→ OV;
 )


IF (MIN B) THEN (

IF ACCB - ACCA < 0 THEN (

-1 → Wd OR ACCB - ACCA → Wd (see text);
 ACCA→ ACCB;

0→ Z; 1→ N; 0→ OV;

)

ELSE (

0→ Wd;

1→ Z; 0→ N; 0→ OV;

)

)

The compare examines the full 72-bit value of the target accumulator and will therefore clamp an overflowed accumulator (variable saturation).

If the target accumulator is less than the limit accumulator, load the target accumulator with the contents of the limit accumulator. For MIN (instruction bit field V = 0, default when not declared), set Wd to -1. For MIN.v (instruction bit field V = 1), write the (signed) value by which the limit is exceeded to Wd:

- Word operation: consider only bits [47:32] of the compare result and write to Wd (destination is also word sized, see note 3). If the limit is exceeded by a value greater than that which can be represented by a signed 16-bit number, saturate the Wd write to the maximum 16-bit negative value (i.e., set Wd[15:0] to 0x8000).
- Long word operation: consider only bits [31:0] of the compare result and write to Wd. If the limit is exceeded by a value greater than that which can be represented by a signed 32-bit number, saturate the Wd write to the maximum negative value (i.e., set Wd to 0x80000000).

The Z and N status bits are set such that a subsequent BLT instruction will take a branch if the limit is exceeded.

If the target accumulator is not less than the limit accumulator, the target accumulator is unaffected, and Wd is cleared. The Z status bit is set such that a subsequent BZ instruction will take a branch.

The OV status bit is always cleared by this instruction.

The ‘L’ bit selects word or long word operation.

The ‘A’ bit specifies the destination accumulator.

The ‘d’ bits select the destination register.

The ‘q’ bits select the destination addressing mode.

The ‘w’ bits define the offset Wb.

The ‘V’ bit defines the result format for Wd.

The ‘L’ bit selects word or long word operation.

The ‘f’ bits select the address of the file register.

The ‘d’ bits select the destination register.

The ‘f’ bits select the address of the file register.

The ‘d’ bits select the destination register.

The ‘f’ bits select the address of the file register.

The ‘s bits select the source register.